Question

所以我做了一个4位加法器，我希望它的端口映射到我正在构建的ALU，但是由于某种原因，端口映射作为错误出现了。我已经尝试了所有方法，更改了变量类型，更改了逻辑，甚至更改了变量名称，但没有任何效果。当我尝试使用端口映射（显示bit0，bit1 ...的行）时，错误弹出，并且该错误抱怨工作'port'和';'。


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Define the input and output signals

ENTITY bit_FA IS
PORT (
    A, B : in unsigned(7 downto 0);
    CI : in std_logic;
    SUM : out unsigned(7 downto 0);
    CO : out std_logic);
END bit_FA;

-- Describe  the  full  adder 's behavior

ARCHITECTURE bit_FA1 OF bit_FA IS
signal tmp: unsigned(8 downto 0);
begin
    tmp <= A + B + ("0" & ci); --trick to promote ci to unsigned
    SUM <= tmp(7 downto 0);
    CO <= tmp(8);
END bit_FA1;

LIBRARY  IEEE;
USE  IEEE.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

-- Define  the  input  and  output  signals
ENTITY FinalLab IS
PORT (
    CLK : in BIT;
    code : in BIT_VECTOR;
    A: in STD_LOGIC_VECTOR (3 downto 0);
    B : inout STD_LOGIC_VECTOR (3 downto 0);
    C, D : out STD_LOGIC_VECTOR (3 downto 0);
    CO : out STD_LOGIC);
END FinalLab;

ARCHITECTURE behave_1 OF FinalLab IS

signal cin : std_logic_vector(3 downto 0);
component bit_FA is
port (
    a, b, c : in std_logic;
    sum, carry : out std_logic);
end component;

BEGIN
process(code)
begin
    if code = "000" then
        --error
        bit0 : bit_FA port map( A(0), B(0), '0', C(0), cin(0));
        bit1 : bit_FA port map ( A(1), B(1), carry(0), C(1), cin(1) );
        bit2 : bit_FA port map ( A(2), B(2), carry(1), C(2), cin(2) );
        bit3 : bit_FA port map ( A(3), B(3), carry(2), C(3), cin(3) );
        CO <= cin(3);
    elsif code = "001" then
        C(0) <= A(3);
        C(1) <= A(2);
        C(2) <= A(1);
        C(3) <= A(0);
    elsif code = "010" then
        --multiplication
        B <= std_logic_vector( unsigned(B) - 1 );
    elsif code = "011" then
        C <= std_logic_vector( unsigned(A) + 1 );
    elsif code = "100" then
        C(0) <= not(A(0) XOR B(0));
        C(1) <= not(A(1) XOR B(1));
        C(2) <= not(A(2) XOR B(2));
        C(3) <= not(A(3) XOR B(3));
    elsif code = "101" then
        C(0) <= not A(0);
        C(1) <= not A(1);
        C(2) <= not A(2);
        C(3) <= not A(3);
    elsif code = "110" then
        C(0) <= A(3);
        C(1) <= A(0);
        C(2) <= A(1);
        C(3) <= A(2);
    elsif code = "111" then
        C(0) <= A(1);
        C(1) <= A(2);
        C(2) <= A(3);
        C(3) <= A(0);
    end if;
end process;

END behave_1;

Answer 1

VHDL代表VHSIC 硬件描述语言。由于它是硬件，因此不能使用if语句等使组件神奇地显示和消失。所有组件都需要一直连接。您可以要做的是实现开关/多路复用器以选择组件的输出。但是，您需要中间信号。

即，需要在架构范围内连接完整的加法器，并在if语句中选择输出

ARCHITECTURE behave_1 OF FinalLab IS
    signal FA_out : std_logic_vector(3 downto 0);
    [...]
begin
    bit0 : bit_FA port map( A(0), B(0), '0', FA_out(0), cin(0));
    bit1 : bit_FA port map ( A(1), B(1), cin(0), FA_out(1), cin(1) );
    bit2 : bit_FA port map ( A(2), B(2), cin(1), FA_out(2), cin(2) );
    bit3 : bit_FA port map ( A(3), B(3), cin(2), FA_out(3), cin(3) );
    [...]
    if code = "000" then
        C <= FA_out;
        CO <= cin(3);
    [...]

注意：CLK输入端口在那里是有原因的……使用它。

VHDL端口映射具有无符号变量的加法器时出错

1 个答案: