如何使用循环简化此Makefile

时间:2019-10-15 14:32:26

标签: makefile

我的Makefile中有这样的行,任何人都可以建议如何为其编写循环,或通过其他任何方式简化它。

OBJS :=

obj-y :=
include cpu/Makefile
OBJS += $(patsubst %,cpu/%, $(obj-y))

obj-y :=
include drivers/Makefile
OBJS += $(patsubst %,drivers/%, $(obj-y))

obj-y :=
include lib/Makefile
OBJS += $(patsubst %,lib/%, $(obj-y))

obj-y :=
include init/Makefile
OBJS += $(patsubst %,init/%, $(obj-y))

...

内部Makefile没有任何目标,仅用于包含目的。例如cpu/Makefile是这样的:

obj-$(CONFIG_XYZ) += something.c
obj-$(CONFIG_ABC) += something_else.c

所有配置都设置为yn

1 个答案:

答案 0 :(得分:2)

让我们分阶段进行吧。

首先,patsubst胜任这项工作; addprefix可以做到:

obj-y :=
include cpu/Makefile
OBJS += $(addprefix cpu/, $(obj-y))

然后请注意,我们可以将“ cpu”作为变量拉出:

DIR=cpu
obj-y :=
include $(DIR)/Makefile
OBJS += $(addprefix $(DIR)/, $(obj-y))

然后使用evalrecipe template or "canned recipe"

define ADD_OBJECTS
obj-y :=
include $(1)/Makefile
OBJS += $$(addprefix $(1)/, $$(obj-y))
endef

$(eval $(call ADD_OBJECTS,cpu))

然后将eval语句放在foreach loop中:

$(foreach DIR,cpu drivers lib init,$(eval $(call ADD_OBJECTS,$(DIR))))