我正在编写一个代码,其中基于输入条件唤起某些序列检测器模块,并根据它们各自的输出来设置最终系统输出。
我尝试了赋值运算符,但我认为它是错误的。
我尝试使用输出reg等更改标识符。
我在同一行中使用<=。
我总是对整个代码进行阻塞。
****
module direction_detection(event1,event2,uni_or_bi_in,event_in,timer_in,
clk,rst,axel_detect,direction_up,direction_down,axel_count);
input event1,event2,event_in,uni_or_bi_in,timer_in,clk,rst;
output direction_up ,direction_down,axel_count;
output reg axel_detect;
reg ticker_ON,ticker_up,event1_pulse,event2_pulse,event1_pcounter,event2_pcounter;
wire concat_events;
wire reset,axel_sq_out;
always @ ( posedge clk)
begin
if(rst==1'b1)
begin
direction_up <= 0'b0;
direction_down <= 0'b0;
axel_count <= 0'b0;
axel_detect <= 0'b0;
reset <= 1'b1;
end
end
timer_delay t1(timer_in,clk,reset,ticker_up);
pulse_detector p1 (event1,clk,event1_pulse,event1_pcounter);
pulse_detector p2 (event2,clk,event2_pulse,event2_pcounter);
assign concat_events = {event1_pulse,event2_pulse};
if ( uni_or_bi_in ==1'b1)
begin
sequence_detector_uniD sdu1( rst,clk,concat_events,axel_sq_out,direction_up,direction_down );
if (axel_sq_out==1'b1 && (direction_up==1'b1 || direction_down==1'b1))
begin
axel_count=axel_count+1; //****
reset = (direction_up || direction_down);
end
else
begin
reset =~(direction_up || direction_down); // ****
end
end
else
begin
sequence_detector_biD sdb1( rst,clk,event_in,event1_pulse,event2_pulse,axel_detect );
if (axel_detect ==1'b1)
begin
axel_count=axel_count+1; // ****
reset=1'b1;
end
else
begin
reset=1'b0; // ****
end
end
endmodule
答案 0 :(得分:1)
您不能像这样有条件地调用模块,也不能在不是generate语句的if-else块中实例化模块。您必须实例化所有模块,然后有条件地使用它们的输出。
您可以尝试以下类似方法,至少可以编译,但是可能还需要解决其他问题。
module direction_detection(
event1,event2,uni_or_bi_in,event_in,timer_in,
clk,rst,axel_detect,direction_up,direction_down,axel_count);
input event1,event2,event_in,uni_or_bi_in,timer_in,clk,rst;
output reg direction_up ,direction_down,axel_count;
output reg axel_detect;
reg ticker_ON,ticker_up,event1_pulse,event2_pulse,
event1_pcounter,event2_pcounter;
wire concat_events;
reg reset,axel_sq_out;
timer_delay t1(timer_in,clk,reset,ticker_up);
pulse_detector p1 (
event1,clk,event1_pulse,event1_pcounter);
pulse_detector p2 (
event2,clk,event2_pulse,event2_pcounter);
sequence_detector_uniD sdu1(
rst,clk,concat_events,axel_sq_out,direction_up,direction_down);
sequence_detector_biD sdb1(
rst,clk,event_in,event1_pulse,event2_pulse,axel_detect);
always @(posedge clk)
begin
if(rst==1'b1)
begin
direction_up <= 0'b0;
direction_down <= 0'b0;
axel_count <= 0'b0;
axel_detect <= 0'b0;
reset <= 1'b1;
end else begin
if (uni_or_bi_in==1'b1)
begin
if (axel_sq_out==1'b1 && (direction_up==1'b1 || direction_down==1'b1))
begin
axel_count <= axel_count+1;
reset <= (direction_up || direction_down);
end
else
begin
reset <= ~(direction_up || direction_down);
end
end
else
begin
if (axel_detect==1'b1)
begin
axel_count <= axel_count+1;
reset <= 1'b1;
end
else
begin
reset <= 1'b0;
end
end
end
end
assign concat_events = {event1_pulse,event2_pulse};
endmodule