Question

运行VWF文件时，我的代码不会模拟输出。

我尝试在不同的时间更改代码，但并不太了解我在做什么错。

            library IEEE;
            use IEEE.STD_LOGIC_1164.ALL;
            use IEEE.STD_LOGIC_UNSIGNED.ALL;

            entity Counter_JM is
            Port (    
                up_down : in std_logic;
                    LED : out std_logic;
                Q   : Buffer integer Range 0 to 7);

            end Counter_JM;

            architecture archi of Counter_JM is

            Begin

                -- up/down counter
                process (up_down)
                begin
                    if (Q=7) then
                        Q<=0;   
                    end if;

                    if (up_down = '1') then
                        Q <= Q + 1; 
                    else   
                        Q<=0;           
                    end if;

                    if (Q=0 or Q=1) then
                        LED <= '0';
                    else 
                        LED <= '1';
                    end if;

                end process;    
            end archi;

在VWF文件上，LED输出应显示高电平4个周期，而低电平2个。

Answer 1

我不知道您为什么使用up_down。但是正如奥尔德法特所说，您没有时钟。我已经简化并修改了您的代码（它对我有效（在modelsim中）：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter_JM is
     Port (   
            clk: in std_logic;
            up_down : in std_logic;
            LED : out std_logic
                );
end Counter_JM;

architecture archi of Counter_JM is


Begin

process (clk)


    variable Q: integer range 0 to 7;

begin

    if rising_edge(clk) then
        -- up/down counter     

        Q := Q + 1;

    if Q=1 or Q=2 then
        LED <= '0';
    else
        LED <= '1';
    end if;

    if Q = 7 then
        Q := 0;
    end if;

    end if;

end process;    

 end archi;

并还创建/生成了一个简单的测试平台here：

`-- Testbench automatically generated online
-- at http://vhdl.lapinoo.net
-- Generation date : 7.6.2019 11:22:53 GMT

library ieee;
use ieee.std_logic_1164.all;

entity tb_Counter_JM is
end tb_Counter_JM;

architecture tb of tb_Counter_JM is

    component Counter_JM
        port (clk     : in std_logic;
              up_down : in std_logic;
              LED     : out std_logic);
    end component;

    signal clk     : std_logic;
    signal up_down : std_logic;
    signal LED     : std_logic;

    constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
    signal TbClock : std_logic := '0';
    signal TbSimEnded : std_logic := '0';

begin

    dut : Counter_JM
    port map (clk     => clk,
              up_down => up_down,
              LED     => LED);

    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

    -- EDIT: Check that clk is really your main clock signal
    clk <= TbClock;

    stimuli : process
    begin
        -- EDIT Adapt initialization as needed
        up_down <= '0';

        -- EDIT Add stimuli here
        wait for 100 * TbPeriod;

        -- Stop the clock and hence terminate the simulation
        TbSimEnded <= '1';
        wait;
    end process;

end tb;

-- Configuration block below is required by some simulators. Usually no need to edit.

configuration cfg_tb_Counter_JM of tb_Counter_JM is
    for tb
    end for;
end cfg_tb_Counter_JM;`

我是VHDL编码的新手，不理解为什么在VWF文件上进行模拟时我的代码为什么不显示输出

1 个答案: