Question

为PWM代码VHDL添加LOOP

下面的代码在将其上传到DE2板上时仅运行一次。

此代码生成8位占空比和周期（00000000）。

我需要帮助的是添加一个循环，使该代码在继续循环中运行，生成PWM信号，直到我选择使用（crl）开关停止它为止。（1或0）：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwm8 is 
port(
    clr : in std_logic;
    clk : in std_logic;
    duty : in std_logic_vector(7 downto 0 );
    period : in std_logic_vector(7 downto 0);
    pwm : out std_logic
    );
end pwm8;

architecture pwm8 of pwm8 is 
    signal count: std_logic_vector(7 downto 0);
    Begin 
    cnt8 : process (clk,clr)
    begin
        if clr = '1' then 
            count <= "00000000";
        elsif clk 'event and clk = '1' then 
            if count = period -1 then
                count <= "00000000";
            else
                count <= count +1;
            end if;
        end if;
    end process cnt8; 

    pwmout: process ( count)
    begin 
        if count  < duty then 
            pwm <='1';
        else 
            pwm <= '0';
        end if;
    end process pwmout;
end pwm8;

如何将循环功能集成到vhdl文件中？

0 个答案: