Question

我了解一些VHDL。

我的目标是拥有4位矢量输入，并将输出发送到以base4数字显示的7段显示器。

例如1111-> 33，1001-> 21

我正在努力将VHDL中的从base2转换为base4。如前所述，当我将base2转换为base4时，我想将其发送到7段显示器中，请您告诉我该怎么做？

Answer 1

二进制很容易转换为任何基于2的幂的数字系统，例如4或8或16。只需按log2(bigger base)对位进行分组。对于以4为底的分组，按log2(4)=2分组：

00->0
01->1
10->2
11->3
1110->32

您只需通过连接导线将长度为X的向量拆分为长度为X/2的向量2即可：

library IEEE;
use IEEE.std_logic_1164.all;

-- 8 binary bit number to 4 base4 numbers
-- binary - is input number
-- d1 is the most significant base-4 digit
-- ...
-- d4 is the least significant base-4 digit

entity BinToBase4 is
port(binary : in STD_LOGIC_VECTOR(7 downto 0);
     d1 : out STD_LOGIC_VECTOR(1 downto 0);
     d2 : out STD_LOGIC_VECTOR(1 downto 0);
     d3 : out STD_LOGIC_VECTOR(1 downto 0);
     d4 : out STD_LOGIC_VECTOR(1 downto 0)
    );
end BinTobase4;

architecture rtl of BinToBase4 is
begin
    d1 <= binary(7 downto 6);
    d2 <= binary(5 downto 4);
    d3 <= binary(3 downto 2);
    d4 <= binary(1 downto 0);
end rtl;

为此测试台：

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench; 

architecture tb of testbench is
component BinToBase4 is
port(
    binary : in STD_LOGIC_VECTOR(7 downto 0);
    d1 : out STD_LOGIC_VECTOR(1 downto 0);
    d2 : out STD_LOGIC_VECTOR(1 downto 0);
    d3 : out STD_LOGIC_VECTOR(1 downto 0);
    d4 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;

    signal num : std_logic_vector(7 downto 0);
    signal d1 : std_logic_vector(1 downto 0);
    signal d2 : std_logic_vector(1 downto 0);
    signal d3 : std_logic_vector(1 downto 0);
    signal d4 : std_logic_vector(1 downto 0);
begin
    b4: BinToBase4 port map(num,d1,d2,d3,d4);
     process
    begin
      num <= "10110001";
      wait for 1 ns;

      assert(d1="10") report "Fail 10" severity error;
      assert(d2="11") report "Fail 11" severity error;
      assert(d3="00") report "Fail 00" severity error;
      assert(d4="01") report "Fail 01" severity error;
      wait;
    end process;
end tb;

您可能需要将d1，d2，d3，d4扩展到4位，以将它们直接连接到7段显示器。使用串联&：

d1 <= "00" & binary(7 downto 6);
d2 <= "00" & binary(5 downto 4);
d3 <= "00" & binary(3 downto 2);
d4 <= "00" & binary(1 downto 0);

别忘了相应地调整矢量大小。

即dx会变成...

signal dx : std_logic_vector(3 downto 0);

7段显示basys3如何使用2位数字？

1 个答案: