Question

我正在通过使用3个不同的过程来开发安全序列检测器，它是FSM。它具有代表输入数字的 num_in （8位）和仅在第一个数字期间必须为1的 first 输入（1位）作为输入。 FSM处于输出固定的状态。如果用户插入3个错误的输入序列，则可能再次发生这种情况。输出由 unlock 信号（如果序列正确，等于'1'）和 warning 信号（如果序列错误，等于'1'）组成），而且由于输入序列是由5个数字组成的，即使其中一个输入错误，它们也必须每5个时钟周期更新一次。第一个过程是：

state_register_p : process(rst, clk)
        begin 
            if rst = '0' then   -- initial state, asynchronous rst
                current_state <= S0;
            elsif (clk'EVENT and clk = '1') then
                if(rst = '0') then
                    current_state <= S0;
                    --errors <= -1;
                else
                    current_state <= next_state;
                    five_cycles <= std_logic_vector(to_unsigned((to_integer(unsigned(five_cycles)) + 1), five_cycles'length));
                    if to_integer(unsigned(five_cycles)) = 5 then
                        five_cycles <= "001";
                    end if;
                 end if;
            end if;
    end process state_register_p;

在此FSM中，我每个时钟都收到一个8位数字，我必须检查它是否按正确的顺序排列，如果不是，在从Beginnig开始的5个周期后，我设置了一个错误。当错误= 3时，FSM进入另一种状态，其中 unlock 固定为0，而 warning 固定为1，直到再次给出复位作为输入，并且FSM从初始S0状态开始。我的测试台代码是这样的：

clk_tb <= (not(clk_tb) and end_sim) after T_CLK / 2; 
rst_tb <= '1' after T_RESET;

d_process: process(clk_tb, rst_tb)
    variable t : integer := 0; 
  begin
    if(rst_tb = '0') then
      num_in_tb <= (others => '0');
      first_tb <= '0';
      t := 0;
    elsif(rising_edge(clk_tb)) then
      case(t) is 
        -- correct
        when 1 => num_in_tb <= "00100100"; first_tb <= '1';  --36
        when 2 => num_in_tb <= "00010011"; first_tb <= '0';  --19
        when 3 => num_in_tb <= "00111000"; first_tb <= '0';  --56
        when 4 => num_in_tb <= "01100101"; first_tb <= '0';  --101
        when 5 => num_in_tb <= "01001001"; first_tb <= '0';  --73

        --invalid because of the num_in (error = 1, but still < 3)
        when 6 => num_in_tb <= "00100100"; first_tb <= '1';  --36
        when 7 => num_in_tb <= "00010011"; first_tb <= '0';  --19
        when 8 => num_in_tb <= "00111000"; first_tb <= '0';  --56
        when 9 => num_in_tb <= "01100100"; first_tb <= '0';  --100
        when 10 => num_in_tb <= "01001001"; first_tb <= '0';  --73

        --invalid because of the two first (blocking condition) 
        when 11=> num_in_tb <= "00100101"; first_tb <= '0';  --37
        when 12=> num_in_tb <= "00100110"; first_tb <= '1';  --38
        when 13=> num_in_tb <= "00100111"; first_tb <= '1';  --39

        --reset is needed
        when 14=> rst_tb <= '0', '1' after T_RESET;  --unknown behavior here

        -- correct
        when 15 => num_in_tb <= "00100100"; first_tb <= '1';  --36
        when 16 => num_in_tb <= "00010011"; first_tb <= '0';  --19
        when 17 => num_in_tb <= "00111000"; first_tb <= '0';  --56
        when 18 => num_in_tb <= "01100101"; first_tb <= '0';  --101
        when 19 => num_in_tb <= "01001001"; first_tb <= '0';  --73

        when 20 => end_sim <= '0';
        when others => null; -- Specifying that nothing happens in the other cases 

      end case;
      t := t + 1;
    end if;
  end process;

我想在T_RESET之后插入14 => rst_tb <='0'，'1'时插入类似的来重置我的FMS。我该怎么做？谢谢

Answer 1

您目前在多个位置开车rst_tb，这是一个冲突。从d_process外部将其删除，然后从灵敏度列表中删除rst_tb。然后，您的if语句将为：

if rising_edge(clk_tb) then ...

您可以在执行重置操作的when 0 =>变量上创建t子句：

when 0 =>
  num_in_tb <= (others=>'0');
  first_tb <= '0';
  t := 0;
  rst_tb <= '0', '1' after T_RESET;

然后，您可以在rst_tb子句中再次驱动when 14 =>。

...

when 14 =>
  rst_tb <= '0', '1' after T_RESET;

...

您必须将T_RESET的期限缩短为clk_tb，否则您的state_register_p流程将开始缺少来自d_process的刺激。

编辑：

library IEEE;
use IEEE.std_logic_1164.all;
library STD;
use STD.textio.all;

entity tb is
end tb;

architecture arch of tb is

constant T_RESET : time := 5 ns;
constant T_CLK   : time := 10 ns;

signal clk_tb    : std_logic := '0';
signal rst_tb    : std_logic := '0';
signal trig_rst  : std_logic := '0';
signal num_in_tb : std_logic_vector(7 downto 0);
signal first_tb  : std_logic := '0';
signal end_sim   : std_logic := '1';

begin

--  rst_tb <= '0','1' after T_RESET;
clk_tb <= (not(clk_tb) and end_sim) after T_CLK / 2; 

--d_process: process(clk_tb, rst_tb)
d_process: process(clk_tb)
  variable t : integer := 0; 
begin
--    if(rst_tb = '0') then
--      num_in_tb <= (others => '0');
--      first_tb <= '0';
--      t := 0;
--    elsif(rising_edge(clk_tb)) then
  if(rising_edge(clk_tb)) then
    case(t) is 
    when 0 =>
      num_in_tb <= (others=>'0');
      first_tb <= '0';
      rst_tb <= '0', '1' after T_RESET;
    -- correct
    when 1 => num_in_tb <= "00100100"; first_tb <= '1';  --36
    when 2 => num_in_tb <= "00010011"; first_tb <= '0';  --19
    when 3 => num_in_tb <= "00111000"; first_tb <= '0';  --56
    when 4 => num_in_tb <= "01100101"; first_tb <= '0';  --101
    when 5 => num_in_tb <= "01001001"; first_tb <= '0';  --73

    --invalid because of the num_in (error = 1, but still < 3)
    when 6 => num_in_tb <= "00100100"; first_tb <= '1';  --36
    when 7 => num_in_tb <= "00010011"; first_tb <= '0';  --19
    when 8 => num_in_tb <= "00111000"; first_tb <= '0';  --56
    when 9 => num_in_tb <= "01100100"; first_tb <= '0';  --100
    when 10 => num_in_tb <= "01001001"; first_tb <= '0';  --73

    --invalid because of the two first (blocking condition) 
    when 11 => num_in_tb <= "00100101"; first_tb <= '0';  --37
    when 12 => num_in_tb <= "00100110"; first_tb <= '1';  --38
    when 13 => num_in_tb <= "00100111"; first_tb <= '1';  --39

    --reset is needed
    when 14 => rst_tb <= '0', '1' after T_RESET;  --unknown behavior here

    -- correct
    when 15 => num_in_tb <= "00100100"; first_tb <= '1';  --36
    when 16 => num_in_tb <= "00010011"; first_tb <= '0';  --19
    when 17 => num_in_tb <= "00111000"; first_tb <= '0';  --56
    when 18 => num_in_tb <= "01100101"; first_tb <= '0';  --101
    when 19 => num_in_tb <= "01001001"; first_tb <= '0';  --73

    when 20 => end_sim <= '0';
    when others => null; -- Specifying that nothing happens in the other cases 

    end case;
    t := t + 1;
  end if;
end process d_process;

end arch;

执行期间重置VHDL

1 个答案: