Question

我将16位STD_LOGIC_VECTOR切成3部分。我想保留前8个MSB，将8个LSB分成2个半字节，以便对其进行一些处理。我可以做所有这些事情，并且处理一切都很好，但是当我尝试将它们全部放到16位STD_LOGIC_VECTOR输出中时，它只是保持UUUU。有没有一种特殊的方法可以将其放回原处？

    signal fullout : std_logic_vector(15 downto 0);
    signal Sbox1 : integer;
    signal Sbox2 : integer;
    signal tophalf : std_logic_vector(7 downto 0);
    signal secondnibble, firstnibble : std_logic_vector(3 downto 0); --break the LSH into 2 nibbles

  begin
   tophalf(7 downto 0) <= LUTin(15 downto 8);
   secondnibble(3 downto 0) <= LUTin(7 downto 4);
   -- Sbox1 <= to_integer(unsigned(secondnibble));
   firstnibble(3 downto 0) <= LUTin(3 downto 0);
   -- Sbox2 <= to_integer(unsigned(firstnibble));

  p1: process(LUTin)
  begin
  fullout(15 downto 8) <= tophalf(7 downto 0);
  fullout(7 downto 4) <= secondnibble(3 downto 0);
  fullout(3 downto 0) <= firstnibble(3 downto 0);

Answer 1

始终初始化输出。在您的情况下，尚不清楚输出的是什么，所以这是我的猜测：

architecture xyz of zyx is
    signal fullout : std_logic_vector(15 downto 0) := (others =>'0');
    signal tophalf : std_logic_vector(7 downto 0):= (others =>'0');
    signal secondnibble, firstnibble : std_logic_vector(3 downto 0):= (others =>'0');
    .....
    begin
    ....
    end xyz;

切片STD_LOGIC_VECTOR并放在一起？

1 个答案: