我有一个范围为0到23的整数数组，它存储了范围为0到2的值 像前一样：
type t_slave_24symbol is array (0 to 23) of integer range 0 to 2;
signal slave_24symbol : t_slave_24symbol;
type nibble_array is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
signal nibble : nibble_array;
signal nibble_full : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
现在我想将此字符串分成3个序列，然后像进行比较
nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
"0001" when slave_24symbol(012)= 200 else
"0010" when slave_24symbol(012)= 020 else
"1111";
但稍后
nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
。 。
最后
nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
& nibble(5) & nibble(6) & nibble(7);
我该怎么办？因为我要分配char 9 10和11等等。
答案 0 :(得分：1)
问题显示了python语法思维。
在std_logic_vector数组中有一个约束整数数组被转换为二进制表示形式。
首先，工作Minimal, Complete, and Verifiable example用于分配一个半字节元素：
library ieee;
use ieee.std_logic_1164.all;
entity depython is
end entity;
architecture foo of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
begin
-- nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
-- "0001" when slave_24symbol(012)= 200 else
-- "0010" when slave_24symbol(012)= 020 else
-- "1111";
-- BECOMES:
nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1, 2, 0) else
"0001" when slave_24symbol(0 to 2) = nyyblet'(2, 0, 0) else
"0010" when slave_24symbol(0 to 2) = nyyblet'(0, 2, 0) else
"1111";
end architecture;
类型t_slave_24symbol已更改为不受约束的数组定义，其中信号slave_24symbol的声明提供了子类型。 （这在-2008中称为无边界数组定义。）
slave_24symbol的切片的索引范围已更改为VHDL语法。在每个条件下求值的表达式的值范围已使用聚合来更改为VHDL语法，该聚合的类型由需要子类型定义的合格表达式提供。子类型声明需要不受约束/不受限制的数组定义。
需要使用合格的表达式来指定子类型，因为数组类型的预定义相等运算符对不受约束的操作数进行运算-您可以测试两个不同长度的数组的相等性，它们将始终不相等。 （在处理空数组时派上用场。）
请注意，字符串文字的类型（例如“ 0010”）由上下文确定，并且元素值（“ 0”，“ 1”）必须与数组类型（此处为std_ulogic）的元素类型（此处为std_ulogic）兼容std_logic_vector）。
这对slave_24symbol的每个元素进行分析，阐述和模拟（使用默认值（0、0、0），每个进程将在初始化期间执行一次，并发赋值语句被细化为等效的顺序赋值语句，包含在流程声明）。
现在，我们讨论如何在新架构中转换nibble的所有元素：
architecture sequential of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1,2,0) else
-- "0001" when slave_24symbol(0 to 2) = nyyblet'(2,0,0) else
-- "0010" when slave_24symbol(0 to 2) = nyyblet'(0,2,0) else
-- "1111";
-- but later
--
-- nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
--
-- . . .
--
-- and at the end
--
-- nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
-- & nibble(5) & nibble(6) & nibble(7);
process (slave_24symbol)
begin
for i in nibble'range loop
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end loop;
end process;
end architecture;
这里使用函数调用来隐藏一些复杂性。循环语句中的顺序赋值语句（顺序语句本身）使用偏移算术来寻址要评估的slave_24symbol的三个约束整数的所有八个切片。
由于该问题表明在条件信号分配（此处为并发信号分配）中分配了一个半字节元素，因此使用generate语句的并发分配版本：
architecture concurrent of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- process (slave_24symbol)
-- begin
-- for i in nibble'range loop
-- nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
-- end loop;
-- end process;
NIBBLE_IT:
for i in nibble'range generate
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end generate;
end architecture;
所有显示的体系结构都进行了分析，精心设计和模拟，证明所有索引和片段都在子类型范围内。
请注意，您也可以将loop语句倒入参数类型为t_slave_24symbol的函数中，并发或顺序执行一个赋值。这也将允许检测不包含3个整数的倍数的参数值（因为类型t_slave_24symbol被声明为无约束/无界）。通过声明新的类型并将t_slave_24symbol和nyyblet的子类型设为新类型，可以避免检测任何参数值：
architecture all_in_one_function of depython is
type c_integer_array is array (natural range <>) of integer range 0 to 2;
subtype t_slave_24symbol is c_integer_array (0 to 23);
signal slave_24symbol: t_slave_24symbol := (
1,2,0, 2,0,0, 0,2,0, 0,0,0, 0,0,1, 0,0,2, 0,1,0, 0,1,1);
signal nibble_full: std_logic_vector (31 downto 0);
function nybble (slave: t_slave_24symbol) return std_logic_vector is
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
variable nib: nibble_array;
subtype nyyblet is c_integer_array (0 to 2);
begin
for i in nib'range loop
if slave(3 * i to 2 + i * 3) = nyyblet'(1, 2, 0) then
nib(i) := "0000";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(2, 0, 0) then
nib(i) := "0001";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(0, 2, 0) then
nib(i) := "0010";
else
nib(i) := "1111";
end if;
end loop;
return nib(0) & nib(1) & nib(2) & nib(3) &
nib(4) & nib(5) & nib(5) & nib(7);
end function;
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
NIBBLE_IT:
nibble_full <= nybble(slave_24symbol);
process
begin
wait for 0 ns;
report "nibble_full = " & to_string (nibble_full);
wait;
end process;
end architecture;
添加了to_string函数以与-2008之前的VHDL版本兼容。信号_slave_24symbol已初始化以证明转换成功：
/ usr / local / bin / ghdl -a depython1.vhdl
/ usr / local / bin / ghdl -e depython
/ usr / local / bin / ghdl -r depython
depython1.vhdl：79：9：@ 0ms :(报告注释）：nibble_full = 00000001001011111111111111111111