Question

我试图用全加法器将两个4位数字相加。我的完整加法器工作正常，但two_number_adder模块正在生成错误。我的代码如下：

    //two bit adder
module three_bit_adder(first_bit, second_bit, carry_in, sum, carry_out);
  input first_bit, second_bit, carry_in;
  output reg sum, carry_out;
  assign sum = (first_bit ^ second_bit) ^ carry_in;
  assign carry_out = (first_bit & second_bit) | (first_bit & carry_in) | (second_bit & carry_in);
endmodule
//add two numbers
module two_number_adder(first_number, second_number, out, carry_out);
  input [3:0] first_number;
  input [3:0] second_number;
  output [3:0] out;
  output reg carry_out;
  reg temp_carry_in, temp_carry_out;
  assign temp_carry_in = 0;
  integer i;
  for(i = 0; i < 4; i = i + 1)
    begin
      three_bit_adder temp(first_number[i], second_number[i], temp_carry_in, out[i], temp_carry_out);
      assign temp_carry_in = temp_carry_out;
    end
  assign carry_out = temp_carry_out;
endmodule

错误提示

genvar缺少生成循环变量i

Answer 1

如果要使用for循环来实例化许多模块，则需要在generate语句中完成。那么该变量必须是gen var。

您的随身携带不会那样工作。您必须为进位位制作一个向量并正确连接它们。就像在实际硬件中一样，模块之间也需要一条“电线”。

wire [4:0] carry;
genvar i;
generate
  for (i=0; i<4; i=i+1)
     three_bit_adder temp(first_number[i], second_number[i],carry[i], out[i], carry[i+1]);

endgenerate

assign carry[0] = 0;
assign carry_out= carry[4];

在Verilog中添加两个4位数字时出错

1 个答案: