Question

我正在尝试对16位ALU进行编码，该ALU具有算术单元，逻辑单元，移位器单元和控制器的组件。当我尝试运行模拟时，出现这些错误。

Vivado Commandslaunch_simulation
[USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Gzuz/Desktop/FinalProject/FinalProject.sim/sim_1/behav/xsim/elaborate.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
Simulationsim_1[VRFC 10-664] expression has 3 elements ; expected 16 ["C:/Users/Gzuz/Desktop/FinalProject/FinalProject.srcs/sources_1/new/ALU16bit.vhd":54]
[XSIM 43-3321] Static elaboration of top level VHDL design unit alu_tb in library work failed.

我做错了什么？我如何获得此结果以运行模拟。我一直在尝试修复代码数小时，但没有运气，因此能提供任何帮助。

--VHDL CODE--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.LogicUnit16Bit;
use work.ArithmeticUnit16bit;
use work.Shift;
use work.MUX_4_TO_1;
use work.ALUControler;

entity ALU16bit is
    Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
           B : in STD_LOGIC_VECTOR(15 downto 0);
           Opcode : in STD_LOGIC_VECTOR(2 downto 0);
           Mode : in STD_LOGIC;
           ALUout : out STD_LOGIC_VECTOR(15 downto 0);
           Cout : out STD_LOGIC);
end ALU16bit;

architecture Behavioral of ALU16bit is

component ArithmeticUnit16bit is
Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
           B : in STD_LOGIC_VECTOR(15 downto 0);
           Op_Sel : in STD_LOGIC_VECTOR(1 downto 0);
           ArithOut : out STD_LOGIC_VECTOR(15 downto 0);
           Cout : out STD_LOGIC);
end component;

component LogicUnit16Bit is 
    Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
       B : in STD_LOGIC_VECTOR(15 downto 0);
       OpCode : in STD_LOGIC_VECTOR(2 downto 0);
       LogicOut : out STD_LOGIC_VECTOR(15 downto 0));
end component;

component Shift is
    Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
       B : in STD_LOGIC_VECTOR(15 downto 0);
       Direction: in STD_LOGIC;
       Op_Type: in STD_LOGIC;
       ShiftOut : out STD_LOGIC_VECTOR(15 downto 0));
end component; 

component MUX_4_TO_1 is
Port (Ain,Bin,Cin,Din: in STD_LOGIC_VECTOR(15 downto 0); 
        Sel:in STD_LOGIC_VECTOR(1 downto 0);
        Zout: out STD_LOGIC_VECTOR( 15 downto 0)); 
end component; 

component ALUControler is
    Port ( Mode : in STD_LOGIC;
       Opcode : in STD_LOGIC_VECTOR(2 downto 0);
       Op_out : out STD_LOGIC_VECTOR(2 downto 0);
       D : out STD_LOGIC;
       T : out STD_LOGIC;
       Sel : out STD_LOGIC_VECTOR(1 downto 0);
       Sel_1 : out STD_LOGIC;
       Sel_Cout : out STD_LOGIC;
       Sel_2 : out STD_LOGIC);
end component;

signal sg_arith: STD_LOGIC_VECTOR(15 downto 0);
signal sg_logic: STD_LOGIC_VECTOR(15 downto 0);
signal sg_shift: STD_LOGIC_VECTOR(15 downto 0);


begin
C0: ArithmeticUnit16bit Port Map(A, B, Opcode, sg_arith);
C1: LogicUnit16Bit port map(A,B,Opcode, sg_logic);
C2: Shift port map(A,B,Mode,Opcode(1), sg_shift);
C3: MUX_4_TO_1 port map(sg_arith, sg_logic, sg_shift, "ZZZZZZZZZZZZZZZZ", Opcode, ALUout);
C4: ALUControler port map(Mode, Opcode(2 downto 0));

end Behavioral;
---------------------



--Test Bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU_TB is
--  Port ( );
end ALU_TB;

architecture Behavioral of ALU_TB is

component ALU16bit is
    Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
       B : in STD_LOGIC_VECTOR(15 downto 0);
       Opcode : in STD_LOGIC_VECTOR(2 downto 0);
       Mode : in STD_LOGIC;
       ALUout : out STD_LOGIC_VECTOR(15 downto 0);
       Cout : out STD_LOGIC);
end component;  

signal A: STD_LOGIC_VECTOR(15 downto 0);
signal B: STD_LOGIC_VECTOR(15 downto 0);
signal Opcode: STD_LOGIC_VECTOR(2 downto 0);
signal Mode: STD_LOGIC;
signal ALUout: STD_LOGIC_VECTOR(15 downto 0);
signal Cout: STD_LOGIC;

begin
uut: ALU16bit port map(A=>A, B=>B, Opcode=>Opcode, Mode=>Mode, ALUout=>ALUout, Cout=>Cout);

process
begin
Mode<='0';
Opcode<="000";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="001";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="010";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="011";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="100";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="101";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="110";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='0';
Opcode<="111";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="000";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="001";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="010";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="011";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="100";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="101";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="110";
A<=x"AAAA";
B<=x"BBBB";
wait for 10ns;
Mode<='1';
Opcode<="111";
A<=x"AAAA";
B<=x"BBBB";
end process;
end Behavioral;

我正在尝试编码16位ALU（使用结构编码）

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