Verilog：Verilog中的综合错误

Question

enter image description here是Verilog编码的初学者。我已经实例化了超声波传感器逻辑和控制逻辑的模块，以查找观察对象的速度。在综合报告视图中，顶部模块的输出参数令人惊讶地接地。 RTL显示连接性，但不显示综合报告。！

让我知道如何解决此问题。正在发送参考代码

topmodule..
module two_sensors_test(clock,reset,pingL,pingR,start,Done,P1_Left,N1_Left,P1_Right,N1_Right);

input clock,reset,start;
output Done;
output P1_Left,N1_Left,P1_Right,N1_Right;
inout pingL,pingR;

// connecting wires
wire [3:0]S1;
wire [3:0]S2;


wire P1_l,N1_l,P1_r,N1_r; 

//sensor intantiation
   top_module Sensor_L(.clock(clock),.reset(reset),.ping1(pingL),.S(S1));
   top_module Sensor_R(.clock(clock),.reset(reset),.ping1(pingR),.S(S2));


// control logic 

   control_gait uut(.clk(clock),.rst(reset),.L_Sb(S1),.R_Sb(S2),.start(start),
   .P_l(P1_l),.N_l(N1_l),.P_r(P1_r),.N_r(N1_r));

// output assignment
assign P1_Left=P1_l;
assign N1_Left=N1_l;
assign P1_Right=P1_r;
assign N1_Right=N1_r;

endmodule 

您好，Oldfart，谢谢您的快速评论。.这里正在更新控制单元代码。.超声波编码在硬件上也能正常工作。但是在实例化以下控制单元时遇到了问题。

module control_gait(clk,rst,L_Sb,R_Sb,start,P_l,N_l,P_r,N_r
    );
    input clk,rst,start;
    input [3:0] L_Sb,R_Sb;
    //output reg  [25:0] step_length;
    output  P_l,N_l,P_r,N_r;

//    reg state;
    reg [25:0]count_reg,count_nxt;
    reg [25:0]Move_count_reg,Move_count_nxt;
     parameter ideal=1'd0;
     reg  [25:0] step_length;

    reg P_Left_reg,N_Left_reg,P_Right_reg,N_Right_reg;
     reg P_Left_nxt,N_Left_nxt,P_Right_nxt,N_Right_nxt;

 always@(posedge clk)
 begin
    if(rst)
        begin

           // state <= ideal;
            count_reg <=26'd0;
            Move_count_reg <=26'd0;
            P_Left_reg<=1'b0; N_Left_reg<=1'b0; P_Right_reg<=1'b0; N_Right_reg<=1'b0;
        end
    else 
        begin

                   // state <= ideal;
                    count_reg <=count_nxt;
                    Move_count_reg <=Move_count_nxt;
                    P_Left_reg <= P_Left_nxt;  N_Left_reg<= N_Left_nxt; 
                    P_Right_reg <=P_Right_nxt ; N_Right_reg <=N_Right_nxt;

        end     
  end 


  always@(*)
      begin
        count_nxt = count_reg;
        Move_count_nxt = Move_count_reg;
          P_Left_nxt         =   P_Left_reg; N_Left_nxt= N_Left_reg; 
             P_Right_nxt        =   P_Right_reg; N_Right_nxt = N_Right_reg; 
           if(start)
                   begin
                     if (( L_Sb == 4'b0001) &&  ( R_Sb == 4'b0001))
                                   begin
                                             count_nxt = count_reg+1'd1;
                                              step_length = count_reg;
                                P_Left_nxt =1'b1;
                                               N_Left_nxt =1'b1;
                                               P_Right_nxt =1'b1; 
                                               N_Right_nxt =1'b1;
                                   end
                    if((L_Sb == 4'b0101 ) && (R_Sb == 4'b0010 ))                 
                                    begin
//                                        Move_count_nxt =count_reg;
//                                        step_length = count_reg;
                                        count_nxt  = 1'd0;

                                        if(Move_count_reg== step_length)
                                                begin
                                                    Move_count_nxt = 26'd0;
                                                      step_length = 26'd0;

                                                end 
                                             else
                                                begin
                                                     Move_count_nxt = Move_count_reg +1'd1;
                                                                     P_Left_nxt =1'b1;
                                                                     N_Left_nxt =1'b0;
                                                                     P_Right_nxt =1'b0; 
                                                                     N_Right_nxt =1'b1;
                                                end     


                                    end

               end
//                   step_length <= count_reg;
     end



// always@(posedge clk)
// begin

//      if(Move_count_reg== step_length)
//        begin
//            Move_count_nxt = 1'b0;

//        end 
//     else
//        begin
//             Move_count_nxt = Move_count_reg +1'd1;
//               P_l= 1'd1;
//               N_l= 1'd0;
//               P_r= 1'd0;
//               N_r= 1'd1;
//        end     

// end   

// assign step_length = count_reg; 
 assign P_l= P_Left_reg;
  assign N_l= N_Left_reg;
 assign  P_r= P_Right_reg;
 assign  N_r= N_Right_reg;

endmodule