Question

我在用VHDL写一个随机数序列发生器时遇到了麻烦。我尝试使用线性方程式，但Xilinx编译器一直在抱怨语法。

代码使用时钟输入，电路板有7个开关，用于输入种子。从那里，它是所有代数。或者我希望如此。

我的代码如下：

entity RandNumSeqGen is
    Port ( clk : in  STD_LOGIC;
           switches: in STD_LOGIC_VECTOR (6 downto 0);
           num : out  STD_LOGIC_VECTOR (0 to 3));
end RandNumSeqGen;

architecture Behavioral of RandNumSeqGen is
constant M : integer := 278200;
constant A : integer := 6521;
constant B : integer := 88977; 
variable rand_f: real :=0.0;
variable rand_d: integer :=0;
variable seed: integer :=0;
seed <= to_integer(signed(switches));

begin
if (clk'event and clk='1') then
    Seed := (seed*A+B) mod M;
    rand_f:=seed/real(M);
    rand_f:=rand_f*1000;
    rand_d:=integer(rand_f) mod 12;
    num<= rand_d;
end if;


end Behavioral;

理想情况下，代码将继续在0到11之间创建一个新的随机数，并将其写入num输出。

错误报告有很多话要说。

也许我如何声明变量有问题？如果你知道需要修理什么，请告诉我。我想学会做得更好。

Line 47: Syntax error near "seed".
Line 50: Syntax error near "then".
Line 51: Syntax error near "mod".
Line 52: Syntax error near ":=".
Line 53: Syntax error near ":=".
Line 54: Syntax error near "mod".
Line 56: Syntax error near "if".
ERROR:ProjectMgmt - 7 error(s) found while parsing design hierarchy.

对于noob问题我很抱歉，我刚刚开始使用VHDL数字变量。到目前为止，我只使用过C和Python

Answer 1

您的代码应该是

library ieee;
use ieee.std_logic_1164.all;

entity RandNumSeqGen is
    Port (
        clk : in  STD_LOGIC;
        switches: in STD_LOGIC_VECTOR (6 downto 0);
        num : out  STD_LOGIC_VECTOR (0 to 3)
    );
end entity;

architecture Behavioral of RandNumSeqGen is
    use ieee.numeric_std.all;
    constant M : integer := 278200;
    constant A : integer := 6521;
    constant B : integer := 88977;
begin
    gen_rand_out: process(clk)
        variable rand_f: real := 0.0;
        variable rand_d: integer := 0;
        variable seed: integer := 0;
    begin
        if rising_edge(clk) then
            -- seed := to_integer(signed(switches)); -- I don't get what you want to do here
            seed := (seed*A+B) mod M;
            rand_f := real(seed)/real(M);
            rand_f := rand_f*1000.0;
            rand_d := integer(rand_f) mod 12;
            num <= std_logic_vector(to_unsigned(rand_d, num'length));
        end if;
    end process;
end architecture;

但这当然不能合成......

使用线性方程生成种子的VHDL-伪随机数？

1 个答案: