Question

我有一个用VHDL开发的基本计算机的代码。当我为I / O设备添加组件时，它无法生成比特流（它完成了合成和实现），给出了以下错误：

[DRC NSTD-1] Unspecified I/O Standard: 54 out of 54 logical ports use I/O
standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific
value. This may cause I/O contention or incompatibility with the board
power or connectivity affecting performance, signal integrity or in
extreme cases cause damage to the device or the components to which it is
connected. To correct this violation, specify all I/O standards. This
design will fail to generate a bitstream unless all logical ports have a
user specified I/O standard value defined. To allow bitstream creation
with unspecified I/O standard values (not recommended), use this command:
set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using
the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this
command to a .tcl file and add that file as a pre-hook for write_bitstream
step for the implementation run. Problem ports: a[15:0], b[15:0],
sop[2:0], result[15:0], c, z, and n.


[DRC UCIO-1] Unconstrained Logical Port: 54 out of 54 logical ports have
no user assigned specific location constraint (LOC). This may cause I/O
contention or incompatibility with the board power or connectivity
affecting performance, signal integrity or in extreme cases cause damage
to the device or the components to which it is connected. To correct this
violation, specify all pin locations. This design will fail to generate a
bitstream unless all logical ports have a user specified site LOC
constraint defined.  To allow bitstream creation with unspecified pin
locations (not recommended), use this command: set_property SEVERITY
{Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs
infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl
file and add that file as a pre-hook for write_bitstream step for the
implementation run.  Problem ports: a[15:0], b[15:0],
sop[2:0],result[15:0], c, z, and n.

我添加的信号是：

signal lcdout           : std_logic;
signal disout           : std_logic;
signal ledout           : std_logic

新组件的实例是：

inst_RegDis: Reg Port map (
     clock    => clock,
     load     => disout,
     datain   => alu_A,
     dataout  => dis
);

inst_RegLed: Reg Port map (
     clock    => clock,
     load     => ledout,
     datain   => alu_A,
     dataout  => led
);

inst_DecoderOut: Decoder_Out Port map(
     data_in => alu_B,
      lcdout => load,
      disout => disout,
      ledout => ledout
);

最后，具有问题端口的组件是：

inst_ALU: ALU Port map (
       a  => alu_A,
       b  => alu_B,
       sop => selALU,
       c  =>  alu_c,
       z  =>  alu_z,
       n  =>  alu_n,
       result => alu_result
       );

当我评论新的信号和组件问题消失时，ALU和解码器输出共享一个信号，但它不会改变ALU组件中的任何内容。有什么可能导致这个问题的想法吗？

Answer 1

问题在于，当已经有一个信号时，我添加了一个信号。当您有一个仅连接到一端的信号时（在这种情况下，lcdout还没有连接到Decoder_out），它会在写比特流中发送此错误，因为它可能导致数据损坏。为什么这个信号对一个不相关的组件（ALU）造成问题仍然困扰着我。

未指定和无约束的逻辑端口Vivado

1 个答案: