Question

module my_delay_mod(
    input [11:0]audio,
    input delay_clk,
    output [11:0]delay_out
    );

    integer i;
    reg [11:0]memory[0:4999];

    always @ (posedge delay_clk) begin 

        memory[0]<=audio;
        for (i=0; i<4999; i=i+1) begin
            memory[i+1]<=memory[i];
        end

    end 

    assign delay_out = memory[4999];

endmodule

Answer 1

Your code will be hard to synthesis. If you want a synthesisable code, I suggest that, you use a RAM based shift register. You can either use the IP's available with the vendor(I know Xilinx have one in Coregen) or make your own(not so complicated).

In a RAM based shift register you don't really shift all the data in every clock cycle. But you have different read and write pointers. The values of these pointers are separated by the delay value(in terms of number of clock cycles).

the steps would be,

create a RAM with delay+2 depth.
keep writing to RAM in every clock cycle and increment the address.
when the write address is equal to delay, keep reading the data from address 0 onward. From now on, the read and write will happen in every clock cycle.
Whenever the end of RAM is reached the write or read addresses are reset to 0.

Answer 2

假设您的delay_clk为20Khz，这与您的mic_i N 的采样率相同，则 U 可以尝试下面的代码 S 。

integer ee;
reg [11:0] memory[0:2020];

always @ (posedge delay_clk) begin 

    memory[0]<=audio;
    for (ee = 0; ee < 2020; ee = ee+1) begin
        memory[ee+1]<=memory[ee];
    end

    delay_out <= memory[2020];
end

这是一些可能对您有帮助的示例代码，但值可能不正确。这应该指向正确的方向。

音频延迟为0.25，我不确定哪个部分是错误的

2 个答案: