Question

我正在尝试开发一个像逻辑计算器一样的代码;我设法编译代码和测试平台没有任何错误。这是代码：

   module AriLogCal(
                    input logic [3:0] OpA, OpB, //Operands A and B. The two numbers we will operate on.
                    input logic [2:0] DoOpt,        //Operator. Determines the operation we will do.
                    input logic EqualTo, AC,        //Interrupts. AC resets, EqualTo transfers data to display.
                    output logic [6:0] S2, S1, S0   //Seven-Segement LEDS. Shows each digit separately.
                 );

logic [7:0] result;                                     //Result. 
Mathematical operation result data is stored here.
logic [3:0] D2, D1, D0;                                 //Digits. Determines 
the number/symbol/deactivation for each respective SevenSeg.

always begin
if(AC)begin //Makes all the numbers display 0 if AC returns TRUE
result=8'b00000000;
S0=7'b1111110;
S1=7'b1111110;
S2=7'b1111110;        
end
else if(EqualTo)begin //Does this stuff if EqualTo returns TRUE

//Part 1: Operation. Decides the relationship between Operand A and B and stores data under "result"
case(DoOpt) 
3'b000:result=OpA+OpB; //Addition
3'b001:begin              //Subtraction
    if(OpB>OpA)
        result=OpB-OpA;
    else
        result=OpA-OpB;
end 
3'b010:result=OpA*OpB; //Multiplication
3'b011:begin                //Division
    if(OpB)
        result=OpA/OpB;
    else
        result=0;
end
3'b100:begin
    if(OpA&&OpB)              //Logical AND
        result=8'b00000001;
    else
        result=8'b00000000;
end
3'b101:begin
    if(OpA||OpB)              //Logical OR
        result=8'b00000001;
    else result=8'b00000000;
end
endcase

//Part 2: Digits. Dissects the value of "result" into its decimal digits and stores them in logic "D"
if(!OpB&&DoOpt==3'b011)      //This will show "Err" on LED displays
D0=4'b1010;
else if(result<10)begin //Single Digit. S1 and S2 is temporarily set to zero
D0=result;
D1=4'b0000;
D2=4'b0000;
end
else if(result<100)begin //Double digit. S2 is temporarily set to zero
D0=result%10;
D1=result/10;
D2=4'b0000;
end
else begin                   //Triple digit. 
D2=result/100;
result=result%100;
D1=result/10;
D0=result%10;
end


//Part 3: Blanks. Adds blanks and negative sign depending on operation type, according to requirements
case(DoOpt)
3'b000:D2=4'b1011;       //Addition deactivates S2
3'b001:begin             
if(OpB>OpA)                 //Subtraction deactivates or shows negative sign 
for S2
    D2=4'b1100;
else
    D2=4'b1011;
end
3'b011:begin                 //Multiplcation is skipped. 
if(!OpB)begin               //Division has two options:
    D0=4'b1010;             //If divider is 0, this will show "Err" on LED 
displays
    D1=4'b1010;
    D2=4'b1010;
end else                        //Otherwise, S2 is deactivated
D2=4'b0000;
end
3'b100:begin                //Logical AND deactivates S2 and S1
    D2=4'b1011;
    D1=4'b1011;
end
3'b101:begin                //Logical OR deactivates S2 and S1
    D2=4'b1011;
    D1=4'b1011;
end
endcase

//Part 4: Display. Prints the digits from "D" onto its respective Seven Segment LED S
case(D0)
 4'b1010: S0<=7'b0000101; //D0=10 means S0 displays R
 4'b1001: S0<=7'b1110011; //9
 4'b1000: S0<=7'b1111111; //8
 4'b0111: S0<=7'b1110000; //7
 4'b0110: S0<=7'b1011111; //6
 4'b0101: S0<=7'b1011011; //5
 4'b0100: S0<=7'b0110011; //4
 4'b0011: S0<=7'b1111001; //3
 4'b0010: S0<=7'b1101101; //2
 4'b0001: S0<=7'b0110000; //1
 4'b0000: S0<=7'b1111110; //0
 endcase
 case(D1)
 4'b1011: S1<=7'b0000000; //D1=11 means S1 deactivates
 4'b1010: S1<=7'b0000101; //D1=10 means S1 displays R
 4'b1001: S1<=7'b1110011; //9
 4'b1000: S1<=7'b1111111; //8
 4'b0111: S1<=7'b1110000; //7
 4'b0110: S1<=7'b1011111; //6
 4'b0101: S1<=7'b1011011; //5
 4'b0100: S1<=7'b0110011; //4
 4'b0011: S1<=7'b1111001; //3
 4'b0010: S1<=7'b1101101; //2
 4'b0001: S1<=7'b0110000; //1
 4'b0000: S1<=7'b1111110; //0
 endcase
 case(D2)
 4'b1100: S2<=7'b0000001; //D2=12 means S2 shows negative sign
 4'b1011: S2<=7'b0000000; //D2=11 means S2 deactivates
 4'b1010: S2<=7'b1001111; //D2=10 means S2 displays E
 4'b1001: S2<=7'b1110011; //9
 4'b1000: S2<=7'b1111111; //8
 4'b0111: S2<=7'b1110000; //7
 4'b0110: S2<=7'b1011111; //6
 4'b0101: S2<=7'b1011011; //5
 4'b0100: S2<=7'b0110011; //4
 4'b0011: S2<=7'b1111001; //3
 4'b0010: S2<=7'b1101101; //2
 4'b0001: S2<=7'b0110000; //1
 4'b0000: S2<=7'b1111110; //0
 endcase
 end
 end
 endmodule

这是当前的测试平台（这是一个较短的版本;我仍然试图找到背后的问题）

`timescale 1ns/1ps
module AriLogCal_tb;
logic [3:0] in_OpA;
logic [3:0] in_OpB;
logic [2:0] in_DoOpt;
logic in_EqualTo;
logic in_AC;
logic [6:0] out_S2, out_S1, out_S0;

AriLogCal AriLogCal_inst0(.OpA(in_OpA), .OpB(in_OpB), .DoOpt(in_DoOpt), 
.EqualTo(in_EqualTo), .AC(in_AC), .S2(out_S2), .S1(out_S1), .S0(out_S0));

initial begin
in_EqualTo=1'b0;
in_AC=1'b0;


in_OpA = 4'b0111; in_OpB = 4'b0010; in_DoOpt = 3'b000; 
in_EqualTo = 1'b0;#100;

$finish;

end
endmodule

这两个文件都能够成功单独编译，没有错误。但是，当我尝试在RTL模拟器中编译它们时，我得到了这些结果：

https://drive.google.com/file/d/0By4LCb9TUml0WWVsZEYtcG03LVk/view?usp=sharing

尽管编译成功，为什么我的搜索结果中仍然会显示“无数据”？我们将不胜感激。提前谢谢。

Answer 1

AriLogCal中没有任何事件/时间阻止器总是阻塞。always begin是一个无限循环。它将不断重新评估并阻止模拟器移动到下一个时间步。

应该更改always_comb begin，它具有继承的时间阻塞，并且仅在时间0和刺激信号发生变化时触发。您可以选择使用Verilog自动敏感度@*（或同义@(*)）并将语句更改为always @* begin。 always_comb优于always @*，因为如果基本综合要求没有分层，则通过编译错误（例如：寄存器仅在一个始终块中分配，没有阻塞@或{{1}始终阻止的语句。）

仅供参考：你不应该在组合逻辑中使用非阻塞（#）分配;阻止（<=）分配是首选。非阻止分配应在=和偶尔使用always_ff。

中使用

System Verilog Testbench波形无数据

1 个答案: