我在创建Reg时似乎需要使用cloneType,但在创建Wire时不需要使用它。有人可以解释这两种情况之间的区别吗? 看起来Wire和Reg应该有类似的界面。
以下是testbench的完整示例:
package ct
import chisel3._
import chisel3.util._
import chisel3.iotesters._
import org.scalatest.{Matchers, FlatSpec}
object TappedShiftRegister {
def apply[ T <: Data]( d : T, n : Int) : Vec[T] = {
val result = Wire( Vec( n+1, d /* why is "d.cloneType" not needed? */))
result(0) := d
for( i<-0 until n) {
val r = Reg( d.cloneType /* Why doesn't just "d" work? */)
r := result(i)
result(i+1) := r
}
result
}
}
class TappedShiftRegisterIfc extends Module {
val io = IO( new Bundle {
val inp = Input( UInt(8.W))
val out = Output( Vec( 5, UInt(8.W)))
})
}
class GenericTSRTest( factory : () => TappedShiftRegisterIfc) extends FlatSpec with Matchers {
it should "meet all PeekPokeTester expectations" in {
chisel3.iotesters.Driver( factory, "firrtl") { c => new PeekPokeTester(c) {
val N = 4
val off = 47
for { i <- 0 until 100} {
poke( c.io.inp, off+i)
expect( c.io.out(0), off+i) // mealy output
step(1)
for { j <- 0 until N if i > j} {
expect( c.io.out(j+1), off+i-j) // moore outputs
}
}
}} should be (true)
}
}
class TSRTest extends GenericTSRTest( () => new TappedShiftRegisterIfc { io.out := TappedShiftRegister( io.inp, 4) })
答案 0 :(得分:1)
似乎最近已修复。
现在你需要在Wire和Reg。
上做cloneType这是:
firrtl: commit f3c0e9e4b268c69d49ef8c18e41c7f75398bb8cf
chisel3: commit 1be90a1e04383675f5b6d967872904ee3dd55faf
firrtl-interpreter: commit 145b9ee89b167c109b732655447b89660908cf87
chisel-testers: commit a6214ffffe761dba9f2eff77463ea58c80d4768a