我在Vivado中基于Vernier方法编写TDC。我的主板是VC707,带有virtex 7核心。编写完vhdl代码后,我开始模拟。不幸的是,我还在学习fpga和vhdl,所以我遇到了一个问题。
起初我想检查我的输入电路,所以我写了一个简单的测试平台来模拟。我生成短时间间隔来检查TDC的这一部分。在我开始模拟之后,我的两个输出是非正式的,其他输出没有意义(应该是高边缘但模拟在输出上显示零)。
输出应该是上升沿。该电路用于为环形振荡器整形信号。
我的vhdl desing:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Uklad_WE is
Port ( Start : in STD_LOGIC;
Stop : in STD_LOGIC;
Reset : in STD_LOGIC;
Pulse_st : out STD_LOGIC;
Pulse_sp : out STD_LOGIC;
Encnt_st : out STD_LOGIC;
Encnt_sp : out STD_LOGIC);
end Uklad_WE;
architecture Behavioral of Uklad_WE is
signal dst1_out : std_logic;
signal dst2_out : std_logic;
signal dsp1_out : std_logic;
signal dsp2_out : std_logic;
signal INV_chain_13_o : std_logic;
signal INV_chain_15_o : std_logic;
signal gate_cnt1_o : std_logic;
signal gate_cnt2_o : std_logic;
signal dcnt1_out : std_logic;
signal dcnt2_out : std_logic;
component ffd
port(
D,CLK,R : in STD_LOGIC;
Q: out STD_LOGIC
);
end component;
component ffd_set
port(
D,S,CLK : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
component INV_chain_15
port(
input : in STD_LOGIC;
output : out STD_LOGIC;
cnt_sig : inout std_logic
);
end component;
component INV_chain_13
port(
input : in STD_LOGIC;
output : out STD_LOGIC;
cnt_sig : inout std_logic
);
end component;
begin
DST1: ffd port map(
D => '1',
CLK => Start,
R => Reset,
Q => dst1_out);
DST2 : ffd_set port map(
D => '0',
CLK => dst1_out,
S => INV_chain_13_o,
Q => dst2_out);
DSP1 : ffd port map(
D => dst1_out,
CLK => Stop,
R => Reset,
Q => dsp1_out);
DSP2 : ffd_set port map(
D => '0',
CLK => dsp1_out,
S => INV_chain_15_o,
Q => dsp2_out);
DCNT1 : ffd port map(
D => '1',
CLK => gate_cnt1_o,
R => Reset,
Q => dcnt1_out);
DCNT2 : ffd port map(
D => '1',
CLK => gate_cnt2_o,
R => Reset,
Q => dcnt2_out);
INV_chain_st : INV_chain_13 port map(
input => dst2_out,
output => INV_chain_13_o,
cnt_sig => gate_cnt1_o);
INV_chain_sp : INV_chain_15 port map(
input => dsp2_out,
output => INV_chain_15_o,
cnt_sig => gate_cnt2_o);
Pulse_st <= dst2_out;
Pulse_sp <= dsp2_out;
Encnt_st <= dcnt1_out;
Encnt_sp <= dcnt2_out;
end Behavioral;
我的测试平台:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity symulacja_tdc_vo is
end symulacja_tdc_vo;
architecture Behavioral of symulacja_tdc_vo is
component Uklad_WE
Port(
Start : in STD_LOGIC;
Stop : in STD_LOGIC;
Reset : in STD_LOGIC;
Pulse_st : out STD_LOGIC;
Pulse_sp : out STD_LOGIC;
Encnt_st : out STD_LOGIC;
Encnt_sp : out STD_LOGIC);
end component;
--inputs
signal Start : STD_LOGIC := '0';
signal Stop : STD_LOGIC := '0';
signal Reset : STD_LOGIC := '0';
--outputs
signal Pulse_st : STD_LOGIC;
signal Pulse_sp : STD_LOGIC;
signal Encnt_st : STD_LOGIC;
signal Encnt_sp : STD_LOGIC;
begin
--uut
uut: Uklad_WE port map(
Start => Start,
Stop => Stop,
Reset => Reset,
Pulse_st => Pulse_st,
Pulse_sp => Pulse_sp,
Encnt_st => Encnt_st,
Encnt_sp => Encnt_sp);
-- stimuluis process
stim_proc1: process
begin
Start <= not Start after 5 ps;
wait for 500 ps;
end process;
stim_proc2: process
begin
Stop <= not Stop after 50 ps;
wait for 500 ps;
end process;
stim_proc3: process
begin
wait for 250 ps;
Reset <= not Reset;
wait for 500 ps;
end process;
end Behavioral;
组件代码:
ffd - ffd with reset
library ieee;
use ieee.std_logic_1164.all;
entity ffd is
port (
D, CLK, R : in std_logic;
Q : out std_logic );
end ffd;
architecture Bech of ffd is
begin
process( CLK, R )
begin
if R = '0' then
Q <= '0';
elsif rising_edge(CLK) then
Q <= D;
end if;
end process;
end Bech;
ffd_set - ffd with set
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ffd_set is
port (
D, CLK, S : in std_logic;
Q : out std_logic );
end ffd_set;
architecture Bech of ffd_set is
begin
process( CLK, S )
begin
if S = '0' then
Q <= '1';
elsif rising_edge(CLK) then
Q <= D;
end if;
end process;
end Bech;
INV_chain_13 - 逆变器链
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity INV_chain_13 is
Port ( input : in STD_LOGIC;
output : out STD_LOGIC;
cnt_sig : inout STD_LOGIC);
end INV_chain_13;
architecture Behavioral of INV_chain_13 is
signal gate_o : std_logic_vector(12 downto 0);
begin
gate_o(0) <= input;
inv_g_chain : for i in 1 to gate_o'high generate
gate_o(i) <= not gate_o(i-1);
end generate;
gate_o(1) <= cnt_sig;
output <= gate_o(12);
end Behavioral;
INV_chain_15 - 也是逆变器链,只有inv的数量是不同的
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity INV_chain_15 is
Port ( input : in STD_LOGIC;
output : out STD_LOGIC;
cnt_sig : inout STD_LOGIC);
end INV_chain_15;
architecture Behavioral of INV_chain_15 is
signal gate_o : std_logic_vector(14 downto 0);
begin
gate_o(0) <= input;
inv_g_chain : for i in 1 to gate_o'high generate
gate_o(i) <= not gate_o(i-1);
end generate;
gate_o(1) <= cnt_sig;
output <= gate_o(14);
end Behavioral;
RTL分析
这是我的设计原理图
模拟
主要问题:
也许它是vhdl代码问题,我还不知道vhdl编程的每一条规则,我希望有经验更好的人可以帮助我。
我认为在ffd中设置和重置有一些问题。我尝试了很多选择,但没有任何帮助。
答案 0 :(得分:0)
首先:你正在学习VHDL,你有一个Virtex-7 ???我现在正在编程VHDL 15年,但通常只使用spartans ... Virtex太贵了。 Restectp。
但无论如何
inv_g_chain : for i in 1 to gate_o'high generate
gate_o(i) <= not gate_o(i-1);
end generate;
你想在这做什么?我希望您想使用逆变器来延迟一些?只是,在VHDL并发分配是瞬时的,所以它不起作用。您应该手动添加延迟。 E.g:
gate_o(i) <= not gate_o(i-1) after 10 ns;
顺便说一句,你知道你可以使用generics,more links来获得可变的逆变器延迟链长吗?然后,您可以将INV_chain_13和INV_chain_15组合成一个实体。
然后你有多个驱动程序用于相同的信号:
gate_o(1) <= not gate_o(0);
和
gate_o(1) <= cnt_sig;
多个驱动程序无法正常运行。而cnt_sig
属于inout类型的是什么? <=
不是双向分配。 VHDL不擅长双向分配,因此尝试不同的方法。
您正在尝试构建异步系统。这是可能的,但非常困难。请考虑先制作同步的东西,以获得一些经验....现在你正试图在第一次驾驶课上做F1。