我正在使用VHDL实现IDEA算法，我的问题在于 keygenerator模块，当我运行模拟器时，我得到了所有的值U. 即使我为它们分配了其他值，也会发出信号。
{
"Entity": {
"MainId":"XFG",
"AlternateIdentifiers" : [
{
"Type":{
"Abbreviation":"ReferenceNumber"
},
"Value":"abc"
}
]
}
}
那是我的测试平台：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keygenerator is
Port ( round : in STD_LOGIC_VECTOR (3 downto 0);
key : in STD_LOGIC_VECTOR (127 downto 0);
keyout1 : out STD_LOGIC_VECTOR (15 downto 0);
keyout2 : out STD_LOGIC_VECTOR (15 downto 0);
keyout3 : out STD_LOGIC_VECTOR (15 downto 0);
keyout4 : out STD_LOGIC_VECTOR (15 downto 0);
keyout5 : out STD_LOGIC_VECTOR (15 downto 0);
keyout6 : out STD_LOGIC_VECTOR (15 downto 0));
end keygenerator;
architecture Behavioral of keygenerator is
SIGNAL key0 : std_logic_vector (127 downto 0);
SIGNAL key1 : std_logic_vector (127 downto 0);
SIGNAL key2 : std_logic_vector (127 downto 0);
SIGNAL key3 : std_logic_vector (127 downto 0);
SIGNAL key4 : std_logic_vector (127 downto 0);
SIGNAL key5 : std_logic_vector (127 downto 0);
SIGNAL key6 : std_logic_vector (95 downto 0);
signal output : std_logic_vector (95 downto 0);
begin
process (round, key)
begin
key0 <= key;
key1 <= key0(102 downto 0) & key0(127 downto 103);
key2 <= key1(102 downto 0) & key1(127 downto 103);
key3 <= key2(102 downto 0) & key2(127 downto 103);
key4 <= key3(102 downto 0) & key3(127 downto 103);
key5 <= key4(102 downto 0) & key4(127 downto 103);
key6 <= key5(102 downto 7);
case round is
when "0000" => output <= key0(127 downto 32);
when "0001" => output <= key0(31 downto 0) & key1(127 downto 64);
when "0010" => output <= key1(63 downto 0) & key2(127 downto 96);
when "0011" => output <= key2(95 downto 0);
when "0100" => output <= key3(127 downto 32);
when "0101" => output <= key3(31 downto 0) & key4(127 downto 64);
when "0110" => output <= key4(63 downto 0) & key5(127 downto 96);
when "0111" => output <= key5(95 downto 0);
when "1000" => output <= key6;
when others => output <= (others => 'X');
end case;
end process;
keyout6 <= output(15 downto 0);
keyout5 <= output(31 downto 16);
keyout4 <= output(47 downto 32);
keyout3 <= output(63 downto 48);
keyout2 <= output(79 downto 64);
keyout1 <= output(95 downto 80);
end Behavioral;