如何在满足条件时退出敏感度过程

时间:2016-10-26 19:37:32

标签: process vhdl conditional-statements

我有检查重置或时钟的代码,如果有时钟,它会在' buff'上执行一些操作。我想做到这一点,以便一旦' buff'等于'键',它将退出进程。我怎么能做到这一点?

PROCESS (clock, reset)
        BEGIN
            IF(reset = '1') THEN
                buff <= (others => '0'); -- set buffer to 0
                op <= (others => '0');   -- set output to 0
            ELSIF(clock'EVENT AND clock = '1') THEN
                op <= ip;  --output displays what was inputted
                buff(31 downto 8) <= buff (23 downto 0); --shift least significant 24 bits
                buff(7 downto 0) <= ip; --set empty 8 bits to input
                IF (buff = key) THEN
                    success <= '1';  --once buff = key, output a green light
                ELSE 
                    success <= '0';
                END IF;
            END IF;
    END PROCESS;

0 个答案:

没有答案