SystemVerilog内存编码风格

Question

我编写了两个版本的单端口同步RAM，具有可变的读/写宽度。但是，第一个设计导致1307 ALM利用率，而第二个设计导致757个ALM利用率，均使用Quartus Prime 16.0.0 Build 211 Lite Edition编译。知道为什么吗？

First vesion：

typedef enum logic [2:0] {CHAR, UCHAR, SHORT, USHORT, INT} DataType;

module Memory(input DataType dataType, input [31:0] storeData, input [6:0] address, input clock, store, write, output logic excep, output [31:0] loadData);
    logic [1:0][1:0][7:0] memory [0:31];

    always_ff @(posedge clock)
        case (dataType)
            CHAR:
                if (store) memory[address[6:2]][address[1]][address[0]] <= storeData[7:0];

                else loadData <= {{24{memory[address[6:2]][address[1]][address[0]][7]}}, memory[address[6:2]][address[1]][address[0]]};

            UCHAR:
                if (store) memory[address[6:2]][address[1]][address[0]] <= storeData[7:0];

                else loadData <= {24'h0, memory[address[6:2]][address[1]][address[0]]};

            SHORT:
                if (address[0] != 1'h0) excep <= 1'h1;

                else if (store) memory[address[6:2]][address[1]] <= storeData[15:0];

                else loadData <= {{16{memory[address[6:2]][address[1]][1][7]}}, memory[address[6:2]][address[1]]};

            USHORT:
                if (address[0] != 1'h0) excep <= 1'h1;

                else if (store) memory[address[6:2]][address[1]] <= storeData[15:0];

                else loadData <= {16'h0, memory[address[6:2]][address[1]]};

            INT:
                if (address[1:0] != 2'h0) excep <= 1'h1;

                else if (store) memory[address[6:2]] <= storeData;

                else loadData <= memory[address[6:2]];
        endcase
endmodule

第二版：

typedef enum logic [2:0] {CHAR, UCHAR, SHORT, USHORT, INT} DataType;

module Memory(input DataType dataType, input [31:0] storeData, input [6:0] address, input clock, store, write, output logic excep, output [31:0] loadData);
    logic [1:0][1:0][7:0] memory [0:31];

    always_ff @(posedge clock)
        case (dataType)
            CHAR:
                if (store)
                    case (address[1:0])
                        1'h0: memory[address[6:2]][0][0] <= storeData[7:0];
                        2'h1: memory[address[6:2]][0][1] <= storeData[7:0];
                        2'h2: memory[address[6:2]][1][0] <= storeData[7:0];
                        2'h3: memory[address[6:2]][1][1] <= storeData[7:0];
                    endcase

                else
                    case (address[1:0])
                        1'h0: loadData <= {{24{memory[address[6:2]][0][0][7]}}, memory[address[6:2]][0][0]};
                        1'h1: loadData <= {{24{memory[address[6:2]][0][1][7]}}, memory[address[6:2]][0][1]};
                        1'h2: loadData <= {{24{memory[address[6:2]][1][0][7]}}, memory[address[6:2]][1][0]};
                        1'h3: loadData <= {{24{memory[address[6:2]][1][1][7]}}, memory[address[6:2]][1][1]};
                    endcase

            UCHAR:
                if (store)
                    case (address[1:0])
                        1'h0: memory[address[6:2]][0][0] <= storeData[7:0];
                        2'h1: memory[address[6:2]][0][1] <= storeData[7:0];
                        2'h2: memory[address[6:2]][1][0] <= storeData[7:0];
                        2'h3: memory[address[6:2]][1][1] <= storeData[7:0];
                    endcase

                else
                    case (address[1:0])
                        1'h0: loadData <= {24'h0, memory[address[6:2]][0][0]};
                        1'h1: loadData <= {24'h0, memory[address[6:2]][0][1]};
                        1'h2: loadData <= {24'h0, memory[address[6:2]][1][0]};
                        1'h3: loadData <= {24'h0, memory[address[6:2]][1][1]};
                    endcase

            SHORT:
                if (address[0] != 1'h0) excep <= 1'h1;

                else if (store)
                    case (address[1])
                        1'h0: memory[address[6:2]][0] <= storeData[15:0];
                        2'h1: memory[address[6:2]][1] <= storeData[15:0];
                    endcase

                else
                    case (address[1])
                        1'h0: loadData <= {{16{memory[address[6:2]][0][1][7]}}, memory[address[6:2]][0]};
                        1'h1: loadData <= {{16{memory[address[6:2]][1][1][7]}}, memory[address[6:2]][1]};
                    endcase

            USHORT:
                if (address[0] != 1'h0) excep <= 1'h1;

                else if (store)
                    case (address[1])
                        1'h0: memory[address[6:2]][0] <= storeData[15:0];
                        2'h1: memory[address[6:2]][1] <= storeData[15:0];
                    endcase

                else
                    case (address[1])
                        1'h0: loadData <= {16'h0, memory[address[6:2]][0]};
                        1'h1: loadData <= {16'h0, memory[address[6:2]][1]};
                    endcase

            INT:
                if (address[1:0] != 2'h0) excep <= 1'h1;

                else if (store) memory[address[6:2]] <= storeData;

                else loadData <= memory[address[6:2]];
        endcase
endmodule