我是VHDL的新手。我为我的项目(一个计时器)创建了一个过程,它意味着两个按钮(M - 增量分钟和S - 增量秒)。我需要去除它们。我熟悉的辩论过程,但我不知道如何在我的项目中实现它。 [编辑] 我的问题是如何在我的项目中实现去抖动?我是否只需创建一个新流程?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
entity Timer is
port(start_stop,M,S : in std_logic; --Start/Stop , Minutes,Seconds
clk : in std_logic; -- clock 1MHz
s1,s2,m1,m2 : out std_logic_vector(3 downto 0)); --BCD representation for seconds and minutes
end Timer;
--}} End of automatically maintained section
architecture Timer of Timer is
begin
P0 : process(M,S,start_stop)
variable temp1,temp2,temp3,temp4 : std_logic_vector(3 downto 0);
variable carry_s,carry_m : std_logic;
begin
if(M = '1' and S = '1')
then
temp1 := "0000";
temp2 := "0000";
temp3 := "0000";
temp4 := "0000";
s1 <= temp1;
s2 <= temp2;
m1 <= temp3;
m2 <= temp4;
end if;--RESET when you press M and S
if(M = '0' and S = '1')
then
temp1 := temp1 + "0001";
if(temp1 = "1010")
then
temp1 := "0000";
carry_s := '1';
else
carry_s := '0';
end if;
if(carry_s = '1')
then
temp2 := temp2 + "0001";
if(temp2 = "0110")
then
temp2 := "0000";
carry_s := '0';
end if;
end if;
s1 <= temp1;
s2 <= temp2;
end if;-- Increment seconds when you press S
if(M = '1' and S = '0')
then
temp3 := temp3 + "0001";
if(temp3 = "1010")
then
temp3 := "0000";
carry_m := '1';
else
carry_m := '0';
end if;
if(carry_m = '1')
then
temp4 := temp4 + "0001";
if(temp4 = "0110")
then
temp4 := "0000";
carry_m := '0';
end if;
end if;
m1 <= temp3;
m2 <= temp4;
end if;-- Increment seconds when you press S
end process P0;
end Timer;
答案 0 :(得分:1)
您需要做的就是创建一个Top Level
模块,并使用Timer
模块和debounce
模块作为组件。接下来使用端口映射,您应该使用debounce
单元连接按钮,使用Timer
单元的输入连接输出。这样的东西
entity TopLevel is
Port ( M: in STD_LOGIC;
S: in STD_LOGIC;
start_stop: in STD_LOGIC;
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
m1, m2, s1, s2: out STD_LOGIC_VECTOR (3 downto 0));
end TopLevel;
architecture Structural of TopLevel is
COMPONENT Timer
PORT(
start_stop, M, S : IN std_logic;
clk : IN std_logic;
s1,s2,m1,m2 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT debouncebutton
PORT(
clk : IN std_logic;
rst : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
signal debounceM, debounceS :std_logic;
begin
timerunit:Timer port map(
start_stop => start_stop,
M =>debounceM,
S => debounceS,
clk => Clk,
s1 => s1,
s2 => s2,
m1 => m1,
m2 => m2 );
debounceM: debouncebutton PORT MAP(
clk => Clk,
rst => Reset,
input => M,
output => debounceM
);
debounceS: debouncebutton PORT MAP(
clk => Clk,
rst => Reset,
input => S,
output => debounceS
);
end Structural;