Question

我有一个3位向上/向下计数器的vhdl代码，但是当我模拟它时不给出任何输出结果，有什么问题？

   library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity counter is
  Port ( rst,clk : in STD_LOGIC;
   up: in bit;
          z : out STD_LOGIC_vector( 2 downto 0 ));
end counter;
architecture Behavioral of Counter is
signal zint:  STD_LOGIC_vector( 2 downto 0 ) ; 
begin
z<= zint;
 process (clk)
begin
if (clk' event and clk='1') then 
if (rst ='1') then 
zint <= "000" ;
end if;
if (zint <= "111" )then zint <= "000";
elsif (up='1') then zint <= zint+1;
else zint <= zint-1;
end if;
end if;
end process;
end Behavioral;

Answer 1

重置时将zint设置为“000”。然后，只要zint不等于“111”，就会再次将其设置为“000”。 zint如何与“000”不同？
您可以完全放弃第一个if条件，计数器将自动从“111”溢出到“000”，反之亦然。

Answer 2

我认为这一行是你的问题：

if (zint <= "111" )then zint <= "000";

你不是这个意思吗？

if (zint = "111" )then zint <= "000";

事实上，你根本不需要上面这一行 - 计数器会自动回绕。（并且，对于倒计时也是如此，无论如何，你没有代码的情况。）

话虽如此，这里还有其他一些改进代码的建议：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use ieee.std_logic_unsigned.all;        -- DON'T USE THIS...
use ieee.numeric_std.all;                  -- ...USE THIS INSTEAD
entity counter is
  Port ( rst,clk : in STD_LOGIC;
   up: in bit;                             -- DID YOU REALLY WANT TYPE 'bit' HERE?
   z : out STD_LOGIC_vector( 2 downto 0 ));
end counter;

architecture Behavioral of Counter is
  signal zint:  unsigned( 2 downto 0 ) ;   -- MAKE THIS TYPE 'unsigned'...
begin
  z<= std_logic_vector(zint);              -- ... AND USE A TYPE CONVERSION HERE
  process (clk)
  begin
    if rising_edge(clk) then               -- '(clk' event and clk='1')' BECAME OLD-FASHIONED in 1993!
      if rst ='1' then                     -- YOU DON'T NEED THE BRACKETS
        zint <= "000" ;                    -- USE INDENTATION!
      --end if;
      --if zint = "111" then zint <= "000";
      elsif up='1' then
        zint <= zint+1;
      else
        zint <= zint-1;
      end if;
    end if;
  end process;
end Behavioral;

VHDL 3位u / d计数器

2 个答案: