将非常数实值表达式​​用于可合成VHDL时出错

时间:2015-12-24 19:52:36

标签: vhdl vivado

 when f9 =>
       if melcol < 128 and framcounter < 2560 then
           temp <= std_logic_vector(signed(framout)*to_signed(melf(melrow,melcol),8));
           firstmelout <= firstmelout + (to_integer(unsigned(temp)))/1000;
           melcol <= melcol+1;
           framcounter <= framcounter+1;
           fstate <= f9;
       elsif melcol = 128 and melrow < 13 and framcounter < 2560 then
           -----MEMORY NEEDED
           framcounter <= framcounter -128;
           melrow <= melrow+1;      --melrow filter number
           melcol <= 0;
           secondmelout <= firstmelout;
           fstate <= f10;
       elsif melcol = 128 and melrow = 13 and framcounter < 2560 then
           ---------MEMORY NEEDED
           framcounter <= framcounter +128;
           melrow <= 0;
           melcol <= 0;
           secondmelout <= firstmelout;
           fstate <= f10;
       elsif framcounter = 2560 then
           flagmel <= '1';
           fstate <= f12;
       else fstate <= f12;
       end if;

   when f10 =>
       varmel <= real(secondmelout);
       --varmel := LOG10(firstmelout);
       --varlogresult := 100*varlogresult;
       wea3(0) <= '1';
       --logresult <= intlogresult;
       fstate <= f11;

我有一个问题是将非常数整数转换为实数。我想采用firstmelout的log10,但需要真正的类型。所以我尝试使用“real()”将其转换为真实,但Vivado返回此错误消息; 不支持非常数实值表达式​​

我尝试了很多东西,但是我无法解决它,我正在等待你的帮助 非常感谢。

1 个答案:

答案 0 :(得分:1)

如评论中所述,您应该使用可合成的固定或浮点类型来定义逻辑,而不是将real类型用于综合应用程序。您可能会发现,在更改逻辑以使用这些新类型的过程中,您需要重新思考如何实现您要实现的目标。

正如其他人在评论中所述,请查看以下资源: