Question

我正在尝试使用VHDL进程为Spartan-S6系列FPGA制作DNA阅读器模块。问题是我的代码无法合成。它适用于模拟，但合成它只是卡住。我还搜索了不可合成的VHDL流程，但我认为我做得对，它必须很好地合成。这是我的流程代码：

FSMOutputController:process(state,readDnaCmd)

variable clkCounter    :unsigned(7 downto 0) := "00000000";

begin

    case state is
        when zeroState =>
            if readDnaCmd = '1' then
                DNA_Read <= '1';
                SR_read   <= '0';
            else
                SR_read   <= '1';
            end if;
        when initState =>
            DNA_Read  <= '0';
            SR_read   <= '1';
            SR_clk    <= DNA_CLK_temp;
            DNA_Shift <= '1';

        when endReadState =>
            DNA_shift <= '0';
            SR_read   <= '0';
        when readState =>
            clkCounter := clkCounter + 1;
            --clkCounter2 <= clkCounter2 + X"01";
            SR_read   <= '0';
    end case;

end process FSMOutputController;

在尝试合成时，这是ISE日志的一部分：

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <testDNALock>.
Related source file is "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd".
WARNING:Xst:647 - Input <CLK_98MHz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'DNAVerify', unconnected in block 'testDNALock', is tied to its initial value (0).
Summary:
no macro.
Unit <testDNALock> synthesized.

它只是停留在这里，并没有去包含我的进程的DNALock文件。另外还有一件事：当我注释掉赋值行时，它将被正确合成：

FSMOutputController:process(state,readDnaCmd)

variable clkCounter    :unsigned(7 downto 0) := "00000000";

begin

    case state is
        when zeroState =>
            if readDnaCmd = '1' then
                --DNA_Read <= '1';
                --SR_read   <= '0';
            else
                --SR_read   <= '1';
            end if;
        when initState =>
            --DNA_Read  <= '0';
            --SR_read   <= '1';
            --SR_clk    <= DNA_CLK_temp;
            --DNA_Shift <= '1';

        when endReadState =>
        --  DNA_shift <= '0';
        --  SR_read   <= '0';
        when readState =>
            clkCounter := clkCounter + 1;
            --clkCounter2 <= clkCounter2 + X"01";
        --  SR_read   <= '0';
    end case;

end process FSMOutputController;

然后报告将是：

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" completed successfully

您可以从pastebin查看我的完整code和log。

Answer 1

我不完全确定它是否是唯一错误的。但是，至少像DNA_CLK_Temp <= not DNA_CLK_Temp after DNA_CLK_period/2;和DNAReady <= '0' after 500 ns;这样的东西无法合成。这意味着大多数代码都会被优化掉，因为你的时钟永远不会改变。

当您模拟代码时，您应该在测试生成时钟等的单元周围安装一个测试平台模块，而不是在实际模块中进行测试。

不可合成的VHDL代码

1 个答案: