VHDL中的位和位向量之间的实际区别是什么？

Question

我一直在努力完成VHDL中的一项任务，我需要尽快完成。任何帮助和/或建议将非常感激。

我的问题如下：所有信号（在下面链接的图中）都被认为是位向量？

diagram =＆gt; http://s014.radikal.ru/i328/1505/06/472c30243696.png

以下是不想编译的代码：

entity sum1_1 is
port(a3,a4: in bit;
q1,q2: out bit);
end sum1_1;
architecture struct of sum1_1 is
begin
q1 <= a3 xor a4;
q2 <= a3 and a4;
end struct;


entity mul2_2 is
port (a1,a2,b1,b2: in bit;
p1,p2,p3,p4: out bit);
end mul2_2;
architecture f_mul2_2 of mul2_2 is
component sum1_1
port(a3,a4: in bit;
q1,q2: out bit);
end component;
signal k2,k3,k4,k5: bit;
begin
p1 <= a1 and b1;
k2 <= a1 and b2;
k3 <= a2 and b1;
k4 <= a2 and b2;
l1: sum1_1 port map (k2,k3,p2,k5);
l2: sum1_1 port map (k4,k5,p3,p4);
end f_mul2_2;


Entity lab32 is
Generic (N:natural:=4);
Port (x,w,y:in bit_vector (1 to N);
l,r,z:out bit_vector (1 to N));
End lab32;
Architecture func of lab32 is
Component mul2_2
port (a1,a2,b1,b2: in bit;
p1,p2,p3,p4: out bit);
end component;
signal g1,g2,g3,g4,g5,g6: bit_vector (1 to N);
begin
lab322: for i in 1 to N generate
first_bit: if (i=1) generate
first: mul2_2 port map (a1=>w(1), a2=>x(1), b1=>y(2), b2=>y(1), p1=>g1(1), p2=>g2(1), p3=>g3(1), p4=>g4(1));
second: mul2_2 port map (a1=>g1(1), a2=>g2(1), b1=>y(4), b2=>y(3), p1=>r(1), p2=>l(1), p3=>g5(1), p4=>g6(1));
end generate first_bit;
middle_bit: if (i>1) and (i<N) generate 
first_m: mul2_2 port map (a1=>w(i), a2=>x(i), b1=>g3(i-1), b2=>g4(i-1), p1=>g1(i), p2=>g2(i), p3=>g3(i), p4=>g4(i));
second_m: mul2_2 port map (a1=>g1(i), a2=>g2(i), b1=>g5(i-1), b2=>g6(i-1), p1=>r(i), p2=>l(i), p3=>g5(i), p4=>g6(i));
end generate middle_bit;
end_bit: if (i=N) generate
first_e: mul2_2 port map (a1=>w(i), a2=>x(i), b1=>g3(i-1), b2=>g4(i-1), p1=>g1(i), p2=>g2(i), p3=>z(2), p4=>z(1));
second_e: mul2_2 port map (a1=>g1(i), a2=>g2(i), b1=>g5(i-1), b2=>g6(i-1), p1=>r(i), p2=>l(i), p3=>z(4), p4=>z(3));
end generate end_bit;
end generate lab322;
end func;


entity lab32test is 
Generic(N:natural:=4); 
end lab32test; 
architecture behavior of lab32test is 
component lab32 
Port(x,w,y:in bit_vector (1 to N);
l,r,z:out bit_vector (1 to N));
end component; 
signal x,w,y:in bit_vector (1 to N); 
signal l,r,z:out bit_vector (1 to N);
begin 
p1: lab32 port map (x,w,y,l,r,z:bit_vector (1 to N)); 

x<='0', 
'0' after 50 ns, 
'0' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'0' after 250 ns,
'0' after 300 ns,
'0' after 350 ns,
'1' after 400 ns,
'1' after 450 ns,
'1' after 500 ns,
'1' after 550 ns,
'1' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns;
w<='0', 
'0' after 50 ns, 
'0' after 100 ns,
'0' after 150 ns,
'1' after 200 ns,
'1' after 250 ns,
'1' after 300 ns,
'1' after 350 ns,
'0' after 400 ns,
'0' after 450 ns,
'0' after 500 ns,
'0' after 550 ns,
'1' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns;
y<='0', 
'0' after 50 ns, 
'1' after 100 ns,
'1' after 150 ns,
'0' after 200 ns,
'0' after 250 ns,
'1' after 300 ns,
'1' after 350 ns,
'0' after 400 ns,
'0' after 450 ns,
'1' after 500 ns,
'1' after 550 ns,
'0' after 600 ns,
'0' after 650 ns,
'1' after 700 ns,
'1' after 750 ns;
end behavior;

我最初的猜测是我在“通用”运算符或测试函数中的某个地方犯了一个错误。

Answer 1

我们这里有语言问题。从VHDL标准的角度来看，您提供的图表与您的问题之间没有任何关系。 bit_vector是bit类型的元素数组。一个位数组的长度可以从null到自然类型中可能的最大值加一（0是最低值）。

type BIT_VECTOR is array (NATURAL range <>)of BIT;

VHDL是强类型的，并且对bit_vector的赋值必须是bit类型的数组，密切相关的类型或具有到bit_vector的隐式类型转换的字符串文字。当两者具有相同的元素类型时，数组类型密切相关。

分配还要求目标的长度和右侧的表达具有相同的长度。

从您的示例代码中理解您的问题的方式存在一些错误。

作为架构声明项找到的信号声明不应该具有模式：

architecture behavior of lab32test is 
component lab32 
Port(x,w,y:in bit_vector (1 to N);
l,r,z:out bit_vector (1 to N));
end component; 
signal x,w,y:in bit_vector (1 to N); 
signal l,r,z:out bit_vector (1 to N);
begin 

这些信号声明应该是

signal x,w,y: bit_vector (1 to N);  -- in 
signal l,r,z: bit_vector (1 to N);  -- out

p1的端口映射同样受到影响。

p1: lab32 port map (x,w,y,l,r,z:bit_vector (1 to N)); 

它应该具有名称或位置元素而没有子类型指示：

p1: lab32 port map (x,w,y,l,r,z); -- :bit_vector (1 to N))

这显示了位置关联。

现在我们收到消息说你的分配＆＃39; 0＆＃39;和＆＃39; 1＆＃39;文字到bit_vectors。

具有复杂波形的x和y的并发信号分配是有缺陷的。正如我们在上面看到的那样，w和y是bit_vectors，但你分配的字符文字被隐式转换为类型bit：

x<='0', 
'0' after 50 ns, 
'0' after 100 ns,
'0' after 150 ns,
'0' after 200 ns,
'0' after 250 ns,
'0' after 300 ns,
'0' after 350 ns,
'1' after 400 ns,
'1' after 450 ns,
'1' after 500 ns,
'1' after 550 ns,
'1' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns;
w<='0', 
'0' after 50 ns, 
'0' after 100 ns,
'0' after 150 ns,
'1' after 200 ns,
'1' after 250 ns,
'1' after 300 ns,
'1' after 350 ns,
'0' after 400 ns,
'0' after 450 ns,
'0' after 500 ns,
'0' after 550 ns,
'1' after 600 ns,
'1' after 650 ns,
'1' after 700 ns,
'1' after 750 ns;
y<='0', 
'0' after 50 ns, 
'1' after 100 ns,
'1' after 150 ns,
'0' after 200 ns,
'0' after 250 ns,
'1' after 300 ns,
'1' after 350 ns,
'0' after 400 ns,
'0' after 450 ns,
'1' after 500 ns,
'1' after 550 ns,
'0' after 600 ns,
'0' after 650 ns,
'1' after 700 ns,
'1' after 750 ns;
end behavior;

这会给您一些分析时间错误，说明您在分配期间出现类型不匹配。那些性格 文字＆＃39; 0＆＃39;和＆＃39; 1＆＃39;值不能转换为bit_vectors。您需要提供可转换值（字符串）的表达式，其长度与x，w和y（长度N）相匹配。

您也不必在x，w和y的波形中使用连续相同的值进行所有预定值更新，只需更改值。

不考虑N的值，您可以使用如下聚合将bit_vectors x，w和y的所有位设置为一个值：

x<=(others => '0'), 
(others => '0') after 50 ns, 
(others => '0') after 100 ns,
(others => '0') after 150 ns,
(others => '0') after 200 ns,
(others => '0') after 250 ns,
(others => '0') after 300 ns,
(others => '0') after 350 ns,
(others => '1') after 400 ns,
(others => '1') after 450 ns,
(others => '1') after 500 ns,
(others => '1') after 550 ns,
(others => '1') after 600 ns,
(others => '1') after 650 ns,
(others => '1') after 700 ns,
(others => '1') after 750 ns;
w<=(others => '0'), 
(others => '0') after 50 ns, 
(others => '0') after 100 ns,
(others => '0') after 150 ns,
(others => '1') after 200 ns,
(others => '1') after 250 ns,
(others => '1') after 300 ns,
(others => '1') after 350 ns,
(others => '0') after 400 ns,
(others => '0') after 450 ns,
(others => '0') after 500 ns,
(others => '0') after 550 ns,
(others => '1') after 600 ns,
(others => '1') after 650 ns,
(others => '1') after 700 ns,
(others => '1') after 750 ns;
y<=(others => '0'), 
(others => '0') after 50 ns, 
(others => '1') after 100 ns,
(others => '1') after 150 ns,
(others => '0') after 200 ns,
(others => '0') after 250 ns,
(others => '1') after 300 ns,
(others => '1') after 350 ns,
(others => '0') after 400 ns,
(others => '0') after 450 ns,
(others => '1') after 500 ns,
(others => '1') after 550 ns,
(others => '0') after 600 ns,
(others => '0') after 650 ns,
(others => '1') after 700 ns,
(others => '1') after 750 ns;

之后您的代码将进行分析。对于为您的设计提供刺激而言，这并不能解决问题。对于N长度为4，这仅提供bit_vectors的十六个可能二进制值中的两个。

对于N = 4，您还可以将字符串文字值组成，这些字符值包含在bit（0和1）类型的字符文字中找到的字符。

例如＆＃34; 0101＆＃34;或＆＃34; 1110＆＃34;。

当然，您可以在某些约束下使用具有N长度的bit_vector类型的表达式。例如一个常数：

constant FIVE: bit_vector(1 to 4) := "0101"; 

您还可以根据N和升序或降序范围管理复杂的聚合表达式。

如果您的设计在分析（编译）后没有按预期运行，请详细说明并模拟我建议您提出单独的问题。