Question

我正在制作一个电路，处理对某些寄存器的读写操作，并使用单个总线在寄存器之间传输数据，问题是当从总线读取时（寄存器正在从总线读取）它运行良好，但是当试图在寄存器中分配一个它不起作用的值。请注意，如果我使用信号写入它将工作!!!

我的代码：

LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.ALL;

-- Entity: Circuit
-- Description: Organizes read and write operation to the bus
-- n is the size of word in a register, default is 16
-- m is the number of selection lines in the decoder, so 2 ^ m
-- is the number of registers in the cicuit

-- data_bus: the bus used to transfer data
-- reg_read: input to a decoder determines which register to read from bus.
-- reg_write: input to a decoder determines which register to write to bus.
-- read: read signal
-- write: write signal
-- Clk: clock
-- Rst: Reset

ENTITY circuit IS
  GENERIC( n : integer := 16; 
           m : integer := 2);
  PORT(data_bus : INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);
       reg_read, reg_write : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0);
       read, write, Clk, Rst : IN STD_LOGIC);

END circuit;


ARCHITECTURE circuit_arch OF circuit IS

-- Tristate buffers
COMPONENT tsb IS
  GENERIC ( n : integer := 16);

  PORT ( E   : IN  STD_LOGIC; 
         Input  : IN  STD_LOGIC_VECTOR (n-1 DOWNTO 0);
         Output : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0));
END COMPONENT;


-- Registers
COMPONENT ndff IS
  GENERIC ( n : integer := 16);
  PORT( Clk,Rst,E : in STD_LOGIC;
        d : IN STD_LOGIC_VECTOR(n-1 dOWNTO 0);
        output : OUT STD_LOGIC_VECTOR(n-1 dOWNTO 0));

END COMPONENT;

-- Decoders
COMPONENT nDecoder IS
  GENERIC ( n : integer := 4);
  PORT(E : IN std_logic;
       S : IN STD_LOGIC_VECTOR( n-1 DOWNTO 0);
       output : OUT std_logic_vector(2 ** n - 1 DOWNTO 0));

END COMPONENT;

TYPE output IS ARRAY (0 TO (2 ** m) - 1) OF STD_LOGIC_VECTOR (n-1 DOWNTO 0);
SIGNAL read_dec, write_dec : STD_LOGIC_VECTOR(2 ** m - 1 DOWNTO 0);
SIGNAL regs_out : output;
SIGNAL test : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN


  -- Generate decoders
  dec1: nDecoder GENERIC MAP(m) PORT MAP(read, reg_read, read_dec);
  dec2: nDecoder GENERIC MAP(m) PORT MAP(write, reg_write, write_dec); 

   -- Generate registers
  LOOP1: FOR i IN 0 TO (2 ** m) - 1 GENERATE

    lbl1: ndff GENERIC MAP(n) PORT MAP(Clk, Rst,read_dec(i),data_bus, regs_out(i));

  END GENERATE;

  -- Generate tristate buffers
  LOOP2: FOR j IN 0 TO (2 ** m) - 1 GENERATE

    lbl2: tsb GENERIC MAP(n) PORT MAP(write_dec(j), regs_out(j), data_bus);

  END GENERATE;

END circuit_arch;

Answer 1

如果您在生成语句中查看lbl1，您将找到端口映射：

 lbl1: ndff generic map(n) port map(clk, rst,read_dec(i),data_bus, regs_out(i));

是位置关联的。虽然组件声明中反映的端口声明显示顺序：

port( clk,rst,e : in std_logic;
        d : in std_logic_vector(n-1 downto 0);
        output : out std_logic_vector(n-1 downto 0));

显示read_dec(i)是寄存器加载启用。

读取缓冲区：

  -- generate tristate buffers
  loop2: for j in 0 to integer(2 ** m) - 1 generate

    lbl2: tsb generic map(n) port map(write_dec(j), regs_out(j), data_bus);

  end generate;

显示write_dec(j)。

检查生成它们的解码显示：

  -- generate decoders
  dec1: ndecoder generic map(m) port map(read, reg_read, read_dec);
  dec2: ndecoder generic map(m) port map(write, reg_write, write_dec);

read对应read_dec，write对应write_dec。

看起来你看起来已经为寄存器加载和寄存器输出缓冲器使能反转了使能。

可能会有更多，但如果没有MVCE，有人回答的问题可以超越基本的眼球和分析。

Paebbels询问目标实现的原因是，对于所有实际目的，三态内部缓冲区通常仅限于ASIC实现。

为什么INPUT不起作用？

1 个答案: