Question

我的节目是

entity mult is
    Port ( a,b : in  STD_LOGIC_VECTOR (07 downto 0);
           p: out  STD_LOGIC_VECTOR (15 downto 0));
end mult;

architecture Behavioral of mult is
signal m1,m6,m8:std_logic_vector(7 downto 4);
signal m2,m3,m5,m7:std_logic_vector(7 downto 0);
signal m4:std_logic_vector(3 downto 0);
signal c,d,x:std_logic;
component fourbitmult 
    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           p : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component csa 
    Port ( a,b : in  STD_LOGIC_VECTOR (07 downto 0);
          cin : in  STD_LOGIC='0';
          s : out  STD_LOGIC_VECTOR (07 downto 0);
          cout : out  STD_LOGIC);
end component;
component rca
port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           carry : out  STD_LOGIC);
end component;
begin
v1:fourbitmult port map(a(3 downto 0),b(3 downto 0),p(3 downto 0),m1(7 downto 4));
v2:fourbitmult port map(a(7 downto 4),b(3 downto 0),m2(7 downto 0));
v3:fourbitmult port map(a(3 downto 0),b(7 downto 4),m3(7 downto 0));
v4:fourbitmult port map(a(7 downto 4),b(7 downto 4),m4(3 downto 0),m8(7 downto 4));
a1:csa port map(m2(7 downto 0),m3(7 downto 0),m5(7 downto 0),c);
a2:csa port map(m1(7 downto 4),m5(7 downto 0),m4(3 downto 0),p(11 downto 4),d);
x<=c or d;
r1:rca port map(m8(7 downto 4),x,p(15 downto 12));


end Behavioral;

我的语法是正确的。我尽力解决这个错误。我仍然得到错误第46行。解析错误，意外的EQ，期待SEMICOLON或CLOSEPAR 什么可能是错的？

错误如“第46行。解析错误，意外情商，期待SEMICOLON或CLOSEPAR”

0 个答案: