为什么组合这些if语句会导致更高的逻辑元素利用率？

Question

我在verilog有一个项目，我在那里跟踪日期。我有以下代码来处理不同长度的月份，除非我弄错了我可以通过oring每个条件和只有一个if语句来组合这些。然而，这将导致再使用1个LE。为什么呢？

        if( ( months == 4 || months == 6 || months == 9 || months == 11 ) && days == 31 && set_state == 0 ) begin
            months = months + 1;
            days = 1;
        end
        else if( months == 2 && years[1:0] == 0 && days == 30 && set_state == 0 ) begin
            months = months + 1;
            days = 1;
        end
        else if( months == 2 && years[1:0] != 0 && days == 29 && set_state == 0 ) begin
            months = months + 1;
            days = 1;
        end
        else if( days == 32 ) begin
            months = months + 1;
            days = 1;               
        end

编辑：这是使用附加LE的原因

    if( ( ( months == 4 || months == 6 || months == 9 || months == 11 ) && days == 31 && set_state == 0 ) ||
        ( months == 2 && years[1:0] == 0 && days == 30 && set_state == 0 ) ||
        ( months == 2 && years[1:0] != 0 && days == 29 && set_state == 0 ) ||
        ( days == 32 ) ) begin
        months = months + 1;
        days = 1;
    end

Answer 1

这两个陈述在逻辑上等同于using the following Boolean law：

A | (~A & B) = A | B 

我认为它与综合工具逻辑最小化算法有关，它不能完全合成相同的电路，尽管它们在逻辑上是等价的。