有没有办法从modelsim模拟中将信号值打印到文件中？

时间：2014-06-20 14:04:22

标签： vhdl modelsim

我需要获取几个信号的值来检查模拟（仿真在Matlab中）。有很多值，我希望将它们放在一个文件中，以便我可以在脚本中运行它并避免手动复制值。

有没有办法自动将多个信号的值打印到文本文件中？

（设计以VHDL实现）

3 个答案:

答案 0 :(得分：5)

首先制作将std_logic和std_logic_vector转换为的函数 string喜欢：

function to_bstring(sl : std_logic) return string is
  variable sl_str_v : string(1 to 3);  -- std_logic image with quotes around
begin
  sl_str_v := std_logic'image(sl);
  return "" & sl_str_v(2);  -- "" & character to get string
end function;

function to_bstring(slv : std_logic_vector) return string is
  alias    slv_norm : std_logic_vector(1 to slv'length) is slv;
  variable sl_str_v : string(1 to 1);  -- String of std_logic
  variable res_v    : string(1 to slv'length);
begin
  for idx in slv_norm'range loop
    sl_str_v := to_bstring(slv_norm(idx));
    res_v(idx) := sl_str_v(1);
  end loop;
  return res_v;
end function;

使用逐位格式的优点是将显示任何非01值 具有确切的std_logic值，而不是例如十六进制 介绍

然后创建从std_logic和...写入字符串的进程 std_logic_vector例如在rising_edge(clk)提交文件，例如：

library std;
use std.textio.all;
...
process (clk) is
  variable line_v   : line;
  file     out_file : text open write_mode is "out.txt";
begin
  if rising_edge(clk) then
    write(line_v, to_bstring(rst) & " " & to_bstring(cnt_1) & " " & to_bstring(cnt_3));
    writeline(out_file, line_v);
  end if;
end process;

上面的示例使用rst作为std_logic，cnt_1和cnt_3作为 std_logic_vector(7 downto 0)。结果输出在＆＃34; out.txt＆＃34;那么：

1 00000000 00000000
1 00000000 00000000
1 00000000 00000000
0 00000000 00000000
0 00000001 00000011
0 00000010 00000110
0 00000011 00001001
0 00000100 00001100
0 00000101 00001111
0 00000110 00010010

答案 1 :(得分：1)

因为有一种方法可以给猫皮肤涂抹：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;

entity changed_morten is
end entity;

architecture foo of changed_morten is

    signal clk: std_logic := '0';
    signal rst: std_logic := '1';
    signal cnt_1: unsigned (7 downto 0);
    signal cnt_3: unsigned (7 downto 0);

    function string_it (arg:unsigned) return string is
        variable ret:    string (1 to arg'LENGTH);
        variable str:  string (1 to 3);  -- enumerated type "'X'"
        alias varg: unsigned (1 to arg'LENGTH) is arg;
    begin
        if arg'LENGTH = 0 then
            ret := "";
        else 
            for i in varg'range loop
                str := std_logic'IMAGE(varg(i));
                ret(i) := str(2);  -- the actual character 
            end loop;
        end if;
        return ret;
    end function;

begin


PRINT:        
    process (clk) is
        variable line_v   : line;
        variable str: string (1 to 3); -- size matches charcter enumeration
        file     out_file : text open write_mode is "out.txt";
    begin
        if rising_edge(clk) then
            str := std_logic'IMAGE(rst);
            write ( line_v,
                    str(2) & " " &
                    string_it(cnt_1) & " " &
                    string_it(cnt_3) & " "
                  );
            writeline(out_file, line_v);
      end if;
    end process;

COUNTER1:
    process (clk,rst)
    begin
        if rst = '1' then
            cnt_1 <= (others => '0');
        elsif rising_edge(clk) then
            cnt_1 <= cnt_1 + 1;
        end if;
    end process;

COUNTER3: 
    process (clk,rst)
    begin
        if rst = '1' then
            cnt_3 <= (others => '0');
        elsif rising_edge(clk) then
            cnt_3 <= cnt_3 + 3;
        end if;
    end process;

RESET:
    process
    begin
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        rst <= '0';
        wait;
    end process;

CLOCK:
    process 
    begin
        wait for 10 ns;
        clk <= not clk;
        if Now > 210 ns then
            wait;
        end if;
    end process;

end architecture;

主要是因为莫滕的表情

"" & std_logic'image(sl)(2);  -- "" & character to get string
ghdl不接受

，它不是索引名称，字符串未命名。

问题似乎是由于缺乏对函数调用的识别（'IMAGE）被识别为索引名称的前缀。对于任何ghdl用户，您都希望使用名为字符串目标的中介来输出属性函数（在string_it函数中显示并在PRINT过程中排成行）。我提交了一份错误报告。

<强>附录

表达Morten的to_bstring（sl：std_logic）返回字符串函数的另一种方法是：

function to_bstring(sl : std_logic) return string is
  variable sl_str_v : string(1 to 3) := std_logic'image(sl);  -- character literal length 3
begin
  return "" & sl_str_v(2);  -- "" & character to get string
end function;

这样做的原因是因为函数调用是动态详细说明的，这意味着每次调用函数时都会创建字符串sl_str_v。

参见IEEE Std 1076-1993 12.5动态详细说明，b。：

  

执行子程序调用涉及详细说明   相应子程序声明的参数接口列表;   这涉及到要创建的每个接口声明的详细说明   相应的形式参数。然后是实际参数   与形式参数相关联。最后，如果指定者了   子程序没有使用'中定义的FOREIGN属性进行修饰   包STANDARD，相应子程序的声明部分   详细阐述了正文以及子程序中的陈述顺序   身体被执行。

IEEE Std 1076-2008,14.6中对子程序调用的动态详细描述进行了一些扩展。

答案 2 :(得分：0)

我想提出一种将std_logic（_vector）转换为字符串的灵活方法：

首先，您可以定义两个函数将std_logic位和数字转换为字符：

FUNCTION to_char(value : STD_LOGIC) RETURN CHARACTER IS
BEGIN
    CASE value IS
        WHEN 'U' =>     RETURN 'U';
        WHEN 'X' =>     RETURN 'X';
        WHEN '0' =>     RETURN '0';
        WHEN '1' =>     RETURN '1';
        WHEN 'Z' =>     RETURN 'Z';
        WHEN 'W' =>     RETURN 'W';
        WHEN 'L' =>     RETURN 'L';
        WHEN 'H' =>     RETURN 'H';
        WHEN '-' =>     RETURN '-';
        WHEN OTHERS =>  RETURN 'X';
    END CASE;
END FUNCTION;

function to_char(value : natural) return character is
begin
    if (value < 10) then
        return character'val(character'pos('0') + value);
    elsif (value < 16) then
        return character'val(character'pos('A') + value - 10);
    else
        return 'X';
    end if;
end function;

现在可以定义两个to_string函数，它们从boolean和std_logic_vector转换为string：

function to_string(value : boolean) return string is
begin
    return str_to_upper(boolean'image(value));  -- ite(value, "TRUE", "FALSE");
end function;

FUNCTION to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') RETURN STRING IS
    CONSTANT int                    : INTEGER               := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
    CONSTANT str        : STRING    := INTEGER'image(int);
    CONSTANT bin_len    : POSITIVE  := slv'length;
    CONSTANT dec_len    : POSITIVE  := str'length;--log10ceilnz(int);
    CONSTANT hex_len    : POSITIVE  := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
    CONSTANT len        : NATURAL   := ite((format = 'b'), bin_len,
                                       ite((format = 'd'), dec_len,
                                       ite((format = 'h'), hex_len, 0)));

    VARIABLE j          : NATURAL   := 0;
    VARIABLE Result     : STRING(1 TO ite((length = 0), len, imax(len, length)))    := (OTHERS => fill);

BEGIN
    IF (format = 'b') THEN
        FOR i IN Result'reverse_range LOOP
            Result(i)    := to_char(slv(j));
            j            := j + 1;
        END LOOP;
    ELSIF (format = 'd') THEN
        Result(Result'length - str'length + 1 TO Result'high) := str;
    ELSIF (format = 'h') THEN
        FOR i IN Result'reverse_range LOOP
            Result(i)    := to_char(to_integer(unsigned(slv((j * 4) + 3 DOWNTO (j * 4)))));
            j            := j + 1;
        END LOOP;
    ELSE
        REPORT "unknown format" SEVERITY FAILURE;
    END IF;

    RETURN Result;
END FUNCTION;

此to_string函数可以将std_logic_vectors转换为二进制（格式=＆＃39; b＆＃39;），二进制（格式=＆＃39; d＆＃39;）和十六进制（格式=＆＃39; h＆＃39; ）。 （可选）如果长度大于0，则可以定义字符串的最小长度;如果std_logic_vector的所需长度小于length，则可以定义填充字符。

以下是必需的辅助函数：

-- calculate the minimum of two inputs
function imin(arg1 : integer; arg2 : integer) return integer is
begin
    if arg1 < arg2 then return arg1; end if;
    return arg2;
end function;

-- if-then-else for strings
FUNCTION ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) RETURN STRING IS
BEGIN
    IF cond THEN
        RETURN value1;
    ELSE
        RETURN value2;
    END IF;
END FUNCTION;

-- a resize function for std_logic_vector
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
    constant  high2b : natural := vec'low+length-1;
    constant  highcp : natural := imin(vec'high, high2b);
    variable  res_up : std_logic_vector(vec'low to high2b);
    variable  res_dn : std_logic_vector(high2b downto vec'low);
begin
    if vec'ascending then
        res_up := (others => fill);
        res_up(vec'low to highcp) := vec(vec'low to highcp);
        return  res_up;
    else
        res_dn := (others => fill);
        res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
        return  res_dn;
end if;
end function;

Ok, this solution looks a bit long, but if you gather some of this functions -- and maybe overload them for several types -- you get an extended type converting system and in which you can convert nearly every type to every other type or representation.
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