Question

module multiplier(prod, busy, mc, mp, clk, start);    
  output [15:0] prod;
  output busy;
  input [7:0] mc, mp;
  input clk, start;

  reg [7:0] A, Q, M;
  reg Q_1;
  reg [3:0] count;
  wire [7:0] sum, difference;

  always @(posedge clk)
  begin
    if (start) begin
      A <= 8'b0;
      M <= mc;
      Q <= mp;
      Q_1 <= 1'b0;
      count <= 4'b0;
    end
    else 
    begin
      case ({Q[0], Q_1})
        2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
        2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
       default: {A, Q, Q_1} <= {A[7], A, Q};
      endcase
      count <= count + 1'b1;
    end
  end

  alu adder (sum, A, M, 1'b0);
  alu subtracter (difference, A, ~M, 1'b1);

  assign prod = {A, Q};
  assign busy = (count < 8);

  initial 
  begin 
    $monitor($time,"prod=%b, busy==%b, mc=%b, mp=%b, clk=%b, start=%b",
                      prod, busy, mc, mp, clk, start);
  end
endmodule

module alu(out, a, b, cin);
  output [7:0] out;
  input [7:0] a;
  input [7:0] b;
  input cin;

  assign out = a + b + cin;
endmodule

----------------------------------测试平台------------ ----------------------------------

module multi_tst_tst;
  reg clk, start;
  reg [7:0] a, b;
  wire [15:0] ab;
  wire busy;

  multiplier multiplier1 (ab, busy, a, b, clk, start);

  initial begin
    clk = 0;
    a =8'b11100000; b =8'b00100000; start = 1; #10 start = 0;
  end
  always #5 clk = !clk;

  //$strobe("ab: %d busy: %d at time=%t", ab, busy, $stime);
endmodule

这是展位乘数的代码我的问题当数据a和b可用时它将开始相乘并继续如果我想检查我的答案我必须做＃80 $停止但我怎么能修改我的代码这样当忙标志变为零我的输出必须在数据线并等待其他输入请给我一些建议我正在尝试这直到昨天我知道手动我可以使用$ finish或$ stop但我不希望我想自动我的模拟停止和另一个输入可用它将再次启动，为什么我使用忙标志

Answer 1

您可以等到忙碌被取消断言。像这样：

  initial begin
    clk = 0;
    a =8'b11100000; b =8'b00100000; start = 1; 
    #10 start = 0;
    @(negedge busy); // waits until busy goes from 1 to 0
    $finish;
  end

对于更详细的测试，测试（几乎）每个可能的输入：

initial begin
  clk = 0;
  for (a=8'd0;a<8'd255;a=a+1) begin
    for (b=8'd0;b<8'd255;b=b+1) begin
      start = 1;
      #10 start = 0;
      @(negedge busy); //wait until multiplier ends
      @(posedge clk);  //waits one clock cycle before moving to the next pair of numbers
    end
  end

端

我的产量各不相同

1 个答案: