VHDL - 设计库不包含单位

Question

我有以下架构：

architecture datapath of DE2_TOP is
begin
U1: entity work.lab1 port map (
    clock => clock_50,
    key => key,
    hex6 => hex6,
    hex5 => hex5,
    hex4 => hex4
);
end datapath;

我收到以下错误：Error (10481): VHDL Use Clause error at DE2_TOP.vhd(276): design library "work" does not contain primary unit "lab1"：U1: entity work.lab1 port map (。有谁知道造成这种情况的原因是什么？

Answer 1

在编译entity之前，您需要至少编译lab1 DE2_TOP