Question

我正在尝试用VHDL构建一个计数器。最终的目标是将“do_count”挂钩到一个按钮。总数将转换为BCD并显示在7段显示屏上。按下按钮，观察数字增量。

我正在使用ModelSim，我可以看到内部“counter_value”正确递增1.但在我的两个测试“do_count”期间，输出信号“total”变为“000X”，然后变为“00X0”。为什么我会收到X'd信号？

我已将“输出＆lt; = current_value”移动到流程内部，流程外部，“if”等内部，仍然是“000X”。

我尝试在流程中使用变量'tmp'。

count_up : process(clk) is
   variable tmp : unsigned (15 downto 0 );
begin
   tmp := current_value;
   -- snip
   if do_count='1' then
      current_value <= tmp + to_unsigned(1,16);
   end if;

我仍然得到“000X”。

完整代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity d_counter is
    port ( rst : in std_logic;
           clk : in std_logic;
           do_count : in std_logic;
           total : out unsigned (15 downto 0)
        );
  end entity d_counter;

architecture counter_arch of d_counter is
  signal current_value : unsigned (15 downto 0) := (others=>'0');
begin
  count_up : process(clk) is
  begin
    if rst='1' then
      current_value <= (others=>'0');
      total <= (others=>'0');
    elsif rising_edge(clk) then
      if do_count='1' then
        current_value <= current_value + to_unsigned(1,16);
      end if;
    end if;
  end process count_up;
  total <= current_value;
end architecture counter_arch;

测试平台：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity test_counter is 
  begin
  end entity test_counter;

architecture run_test_counter of test_counter is

  signal t_rst : std_logic := '1';
  signal t_clk : std_logic := '0';
  signal t_do_count : std_logic;
  signal t_total : unsigned( 15 downto 0 );

  component d_counter is
    port ( rst : in std_logic;
           clk : in std_logic;
           do_count : in std_logic;
           total : out unsigned( 15 downto 0 )
        );
  end component d_counter;

begin
  uut : d_counter
    port map( rst => t_rst,
      clk => t_clk,
      do_count => t_do_count,
      total => t_total );

    clock : process is 
    begin

        t_clk <= '0'; wait for 10 ns;
        t_clk <= '1'; wait for 10 ns;
    end process clock;

    stimulus : process is
    begin
      t_rst <= '1';
      t_do_count <= '0';
      t_total <= (others =>'0');
      wait for 15 ns;

      t_rst <= '0';
      wait for 10 ns;

      t_do_count <= '1';
      wait for 10 ns;

      t_do_count <= '0';
      wait for 10 ns;

      t_do_count <= '1';
      wait for 10 ns;

      t_do_count <= '0';
      wait for 10 ns;

      wait;

    end process stimulus;
end architecture run_test_counter;

2012年10月3日更新。两个答案都有帮助。在流程中移动“total＆lt; = current_value”（来自@simon）并删除额外的“t_total＆lt; =（其他=＆gt;'0'）;” （来自@ peter-bennett）我的测试平台是必需的。我必须做两件事来摆脱X的。

Answer 1

您的代码使用“total”编写多驱动。您应该删除流程计数中的分配。

count_up : process(clk) is
  begin
    if rst='1' then
      current_value <= (others=>'0');
      total <= (others=>'0');  --> Remove it
    elsif rising_edge(clk) then
      if do_count='1' then
        current_value <= current_value + to_unsigned(1,16);
      end if;
     end if;
  end process count_up;

  total <= current_value; -- Keep it

Answer 2

看起来你的错误在你的测试平台上。信号t_total已映射到您的计数器组件的total输出，但您正在使用t_total <= (others => '0')分配给它写信。如果你删除它，我认为你的问题将会消失。

  uut : d_counter
    port map( rst => t_rst,
      clk => t_clk,
      do_count => t_do_count,
      total => t_total );

    clock : process is 
    begin

        t_clk <= '0'; wait for 10 ns;
        t_clk <= '1'; wait for 10 ns;
    end process clock;

    stimulus : process is
    begin
      t_rst <= '1';
      t_do_count <= '0';
      t_total <= (others =>'0'); <-- Do not assign to t_total (its an output)

给出X的VHDL计数器结果

2 个答案: