如何通过uvm工厂填充动态数组

时间:2019-05-14 20:10:52

标签: arrays dynamic system-verilog uvm

您好,我有这样的代码,参数NUM_MASTERS和NUM_SLAVES在配置对象中定义:

class abc extends uvm_scoreboard;
configuration cfg;
wrapper_class master[]; //i am instantiating a dynamic array of class objects, one each for all masters and another for slaves 
wrapper_class slave[];
extern function new(string name = "abc", uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
endclass


function abc::new(string name = "abc", uvm_component parent = null);
super.new(name, parent);
end
function void abc::build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db#(config_type)::get)this."*","configuration", cfg);
//this is where the error is happening
for(int i = 0; i < cfg.NUM_MASTERS : i++) 
  masters[i] = wrapper_class::type_id::create($sformatf("masters[%0d]",i),this);
for(int i = 0;i < cfg.NUM_SLAVES; i++) 
  slaves[i] =wrapper_class::type_id::create($sformatf("slaves[%0d]",i),this);
endfunction

有人可以告诉我如何填充这些动态数组吗?我必须从构建阶段开始执行它们,因为只有那时我才能从cfg对象访问NUM_MASTERS和NUM_SLAVES。非常感谢您的任何帮助/建议。谢谢。

1 个答案:

答案 0 :(得分:1)

访问动态数组之前,您需要new

function void abc::build_phase(uvm_phase phase);
  super.build_phase(phase);
  uvm_config_db#(config_type)::get)this."*","configuration", cfg);
  masters = new[cfg.NUM_MASTERS];
  foreach( masters[i] ) 
    masters[i] = wrapper_class::type_id::create($sformatf("masters[%0d]",i),this);
  slaves = new[cfg.NUM_SLAVES];
  foreach( slaves[i] )
    slaves[i] =wrapper_class::type_id::create($sformatf("slaves[%0d]",i),this);
endfunction