Question

我试图在Verilog中进行Nand2Tetris的练习。我从所有较简单的门开始，先生成一个门和一个测试台，然后用iverilog对其进行编译。但是，我在创建RAM Gate时注意到，随着RAM Gate的增大，文件将呈指数增长，并且编译时间确实很长。例如，RAM16K是2.5 GB，需要大约两个小时才能编译。

我不知道该怎么做，因为我需要测试更复杂的设计（例如CPU），但是编译需要几天的时间。是否有人对问题的根源和解决方案有任何了解？我需要的主要是测试它们是否确实有效。

RAM16K的示例代码如下：

`include "RAM4K.v"
`include "DMux4Way.v"

module RAM16K(out, x, load, address);

   input [15:0] x;
   input [13:0] address;
   input load;
   output [15:0] out;

   wire [15:0] out1, out2, out3, out4;
   wire load1, load2, load3, load4;

   DMUX4WAY g1(load1, load2, load3, load4, load, address [13:12]);

   RAM4K g2(out1,x,load1,address[11:0]);
   RAM4K g3(out2,x,load2,address[11:0]);
   RAM4K g4(out3,x,load3,address[11:0]);
   RAM4K g5(out4,x,load4,address[11:0]);

   MUX4WAY16 g10(out, out1, out2, out3, out4, address [13:12]);

endmodule

还有test_RAM16K.v：

module test();
  reg signed [15:0] x;
  reg load;
  reg [13:0] address;
  wire signed [15:0] out;

  RAM16K test_RAM16K(out, x, load, address);

  // define like a function
  `define m(changes) changes; \
    #1 $display("| %2g+  | %d |  %b  |  %d  | %d |",$time/2,x,load,address,out);\
    #1 $display("| %2g   | %d |  %b  |  %d  | %d |",$time/2,x,load,address,out);

  `define eval(changes) changes; #1 $display("| %2g   | %d |  %b  |  %d  | %d |",$time/2,x,load,address,out);


  initial
    begin
      $display("| time |   x    |load | address |  out   |");
    end

  initial begin

    `m(x = 0; load = 0; address = 0)
    `m(x = 0; load = 1; address = 0)
    `m(x = 4321; load = 0; address = 0)
    `m(x = 4321; load = 1; address = 4321)
    `m(x = 4321; load = 0; address = 0)

    `m(x = 12345; load = 0; address = 12345)
    `m(x = 12345; load = 1; address = 12345)
    `m(x = 12345; load = 0; address = 12345)

    `m(x = 16383; load = 1; address = 16383)
    `m(x = 16383; load = 0; address = 16383)
    `m(x = 16383; load = 0; address = 12345)

    `m(x = 21840; load = 1; address = 10920)
    `m(x = 21841; load = 1; address = 10921)
    `m(x = 21842; load = 1; address = 10922)
    `m(x = 21843; load = 1; address = 10923)
    `m(x = 21844; load = 1; address = 10924)
    `m(x = 21845; load = 1; address = 10925)
    `m(x = 21846; load = 1; address = 10926)
    `m(x = 21847; load = 1; address = 10927)

    `eval(x = 21845; load = 0; address = 10920)
    `eval(x = 21845; load = 0; address = 10921)
    `eval(x = 21845; load = 0; address = 10922)
    `eval(x = 21845; load = 0; address = 10923)
    `eval(x = 21845; load = 0; address = 10924)
    `eval(x = 21845; load = 0; address = 10925)
    `eval(x = 21845; load = 0; address = 10926)
    `eval(x = 21845; load = 0; address = 10927)

    `m(x = -21846; load = 1; address = 10920)
    `m(x = -21846; load = 0; address = 10920)

    $finish;
  end
endmodule

感谢您的帮助，非常感谢！

编辑1：这些是DMUX4WAY和MUX4WAY16的文件：

DMUX4WAY.v

`include "DMux.v"

module DMUX4WAY(w, x, y, z, in, sel);
    input in;
    input [1:0] sel;
    wire tmp1, tmp2, tmp3, tmp4;
    output w, x, y, z;

    DMUX g1(tmp1, tmp2, in, sel[0]);
    DMUX g2(tmp3, tmp4, in, sel[1]);
    AND g3(w, tmp1, tmp3);
    AND g4(x, tmp2, tmp3);
    AND g5(y, tmp1, tmp4);
    AND g6(z, tmp2, tmp4);

endmodule

和MUX4WAY16.v

`include "Mux16.v"

module MUX4WAY16(out, w, x, y, z, sel);

  input [15:0] w, x, y, z;
  input [1:0] sel;

  wire [15:0] tmp1, tmp2;
  wire not_sel;

  output [15:0] out;

  NOT g1(not_sel, sel[0]);
  MUX16 g3(tmp1, w, x, sel[0]);
  MUX16 g4(tmp2, z, y, not_sel);

  MUX16 g2(out, tmp1, tmp2, sel[1]);

endmodule

Iverilog编译花费的时间太长，而且文件很大

0 个答案: