Question

我有VHDL代码，其中包含要模拟的INs，OUTs和内部SIGNAL常数，例如计数器。我已经看了网上的示例，但只看到Modelsim监视IN和OUT。但是，我也想看看计数器等内部信号。我看到一个人只写模拟代码。我需要以下简单示例：一个带有一些IN和OUT以及一些内部信号的代码。一个简单的通用TB代码，仅增加clk或类似的增量。我看到了一个看起来正确的示例，但是当我将其修改为我的代码时，内部信号在Modelsim中未定义。我可能会遗漏一些东西，但我的理解是Modelsim的一个重要功能是编写一个带有时钟的通用测试平台，并使用它来查看我的逻辑直方图。随着代码的进行，您只需要根据需要向tb添加变量。如果有人在原始代码和tb中都有一些通用代码或代码位置，那么他们将共享将非常有帮助。谢谢

Answer 1

我从来没有遇到过让modelim将内部信号绘制到波形上的问题。我只是将信号从“对象”窗口拖放到“波形”窗口上。

这是一个简单的例子。这是TestModule.vhd：

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity TestModule is
port (
          ip_sl_ClkIn                : in std_logic;
          ip_slv_InputVal            : in std_logic_vector(7 downto 0);
          ip_sl_InputValid           : in std_logic;

          op_slv_OutputVal           : out std_logic_vector(7 downto 0);
          op_sl_OutputValid          : out std_logic
);
end TestModule;


architecture Behavioral of TestModule is

  --==========================
  --== INTERNAL SIGNALS
  --==========================
  signal s_slv_InputNibbleSwap_1d : std_logic_vector(7 downto 0) := (others => 'X');
  signal s_slv_Inverted_2d : std_logic_vector(7 downto 0) := (others => 'X');

  signal s_sl_InputValid_1d : std_logic := '0';
  signal s_sl_InputValid_2d : std_logic := '0';

begin


   RegisterProc : process(ip_sl_ClkIn)
    begin
      if(rising_edge(ip_sl_ClkIn)) then

      --Clock Cycle 1:
      --=======================
      --Take the input and swap nibble locations
      s_slv_InputNibbleSwap_1d <= ip_slv_InputVal(3 downto 0) & ip_slv_InputVal(7 downto 4);
      s_sl_InputValid_1d       <= ip_sl_InputValid;

      --Clock Cycle 2:
      --=======================          
      --Invert the bits
      s_slv_Inverted_2d        <= not(s_slv_InputNibbleSwap_1d);
      s_sl_InputValid_2d       <= s_sl_InputValid_1d;

      end if; --rising_edge(ip_sl_ClkIn)
    end process RegisterProc;



    --Route Outputs:
    --=====================
    op_slv_OutputVal  <= s_slv_Inverted_2d;
    op_sl_OutputValid <= s_sl_InputValid_2d;

end Behavioral;

这是测试平台TestModule_tb.vhd：

 LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
  use std.textio.all;
ENTITY TestModule_tb IS
END TestModule_tb;

architecture behavior of TestModule_tb is

-- Component Declaration
-------------------------
  component TestModule
  Port ( 
        ip_sl_ClkIn : in std_logic;
        ip_slv_InputVal : in std_logic_vector ( 7 downto 0 );
        ip_sl_InputValid : in std_logic;
        op_slv_OutputVal : out std_logic_vector ( 7 downto 0 );
        op_sl_OutputValid : out std_logic
    );
  end component;



--Signals Driven by Entity: TestModule
-------------------------
    signal s_slv_OutputVal : std_logic_vector ( 7 downto 0 );
    signal s_sl_OutputValid : std_logic;


--Test Stimulus Signals:
-------------------------
    signal s_sl_ClkIn : std_logic;
    signal s_slv_InputVal : std_logic_vector ( 7 downto 0 );
    signal s_sl_InputValid : std_logic;


BEGIN

--Component Instantiation
    uut : TestModule
    Port Map (
        ip_sl_ClkIn         => s_sl_ClkIn   ,  --in std_logic
        ip_slv_InputVal     => s_slv_InputVal   ,  --in std_logic_vector ( 7 downto 0 )
        ip_sl_InputValid    => s_sl_InputValid   ,  --in std_logic
        op_slv_OutputVal    => s_slv_OutputVal   ,  --out std_logic_vector ( 7 downto 0 )
        op_sl_OutputValid   => s_sl_OutputValid     --out std_logic
    );


    clkProc : process
    begin
        s_sl_ClkIn <= '1';
        wait for 10 ns;
        s_sl_ClkIn <= '0';
        wait for 10 ns;
    end process;


MainTestProcess : Process
Begin

     s_slv_InputVal <= (others => '0');
     s_sl_InputValid <= '0';
     wait for 100 ns; 

     wait until rising_edge(s_sl_ClkIn); wait for 1 ps;
     s_slv_InputVal <= X"AB";
     s_sl_InputValid <= '1';

     wait until rising_edge(s_sl_ClkIn); wait for 1 ps;
     s_slv_InputVal <= X"FF";
     s_sl_InputValid <= '0';     

     wait for 100 ns;

    --Not a failure, but stops the simulation
    assert false report "<---- NOT a failure. Testbench Complete" severity failure;

    wait; -- Will wait forever
end process;

END;

这里是用于编译和仿真的modelim DO文件，TestModule_tb.do：

vlib work
vcom -reportprogress 300 -work work TestModule.vhd
vcom -reportprogress 300 -work work TestModule_tb.vhd 
vsim -gui work.testmodule_tb
do TestModule_tb_wave.do
run -all

这是modelsim波形DO文件TestModule_tb_wave.do：

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testmodule_tb/uut/ip_sl_ClkIn
add wave -noupdate /testmodule_tb/uut/ip_slv_InputVal
add wave -noupdate /testmodule_tb/uut/ip_sl_InputValid
add wave -noupdate /testmodule_tb/uut/op_slv_OutputVal
add wave -noupdate /testmodule_tb/uut/op_sl_OutputValid
add wave -noupdate /testmodule_tb/uut/s_slv_InputNibbleSwap_1d
add wave -noupdate /testmodule_tb/uut/s_slv_Inverted_2d
add wave -noupdate /testmodule_tb/uut/s_sl_InputValid_1d
add wave -noupdate /testmodule_tb/uut/s_sl_InputValid_2d
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {90738 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 331
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {231001 ps}

我需要modelim来查看内部变量

1 个答案: