Question

我是VHDL的新手，并希望出于学习目的而使用该语言

加法器的代码，例如：

library ieee ;
use ieee.std_logic_1164.all;

entity add is
 Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    pin : in STD_LOGIC;
    S : out STD_LOGIC;
    pi : out STD_LOGIC);
end add;

architecture gate_level of add is

begin

 S <= a XOR b XOR pin ;
 pi <= (a AND b) OR (pin AND a) OR (pin AND b) ;

end gate_level;

对于解复用器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DMS is
port(d : in std_logic;
     a : in std_logic_vector(2 downto 0);
     q : out std_logic_vector(7 downto 0)
     );
end DMS;

architecture Demultiplexer of DMS is
begin
    process(d, a)
    begin
    if (d = '1') then
        case a is
            when "000" => q <= "10000000";
            when "001" => q <= "01000000";
            when "010" => q <= "00100000";
            when "011" => q <= "00010000";
            when "100" => q <= "00001000";
            when "101" => q <= "00000100";
            when "110" => q <= "00000010";
            when "111" => q <= "00000001";
            when others => q <= "00000000";
        end case;
    end if;
    end process;
end architecture Demultiplexer;

如何连接，例如使用VHDL语言添加和解复用器？

带解复用器和加法器的VHDL方案仿真

0 个答案: