Question

使用gezel软件，我从这个fdl代码创建了一个vhdl文件：

dp delay_collatz_rev ( 
    in start : ns(1) ; in x0 : ns(16) ; 
    out done : ns(1) ; out delay : ns(16)) 
{   reg r : ns(32) ; 
    reg d : ns(16) ; 
    reg stop : ns(1) ; 
    sig x : ns(32) ; 
    sig d0, dd : ns(16) ; 
    always { x = start ? x0 : r ; 
          r = x[0] ? x + (x >> 1) + 1 : x >> 1 ; 
          done = ( x == 1 ) | ( stop & ~start ) ; 
          stop = done ; 
          dd = 1 + x[0] ; 
          d0 = start ? 0 : d ; 
          d = done ? d0 : d0 + dd ; 
          delay = d ; 
}   }

但是当我尝试在Quartus软件上编译这段代码时，我在第124行得到了这个错误，即“sig_10＆lt; = unsigned（'1'）+ unsigned（x（0））;”

错误（10647）：delay_collatz_rev.vhd上的VHDL类型推理错误（124）：表达式类型不明确 - “std_ulogic”或“bit”是两种可能的匹配

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
--use work.std_logic_arithext.all;


-- datapath entity
entity delay_collatz_rev is
port(
     start                  : in  std_logic;
     x0                     : in  std_logic_vector(15 downto 0);
     done                   : out std_logic;
     delay                  : out std_logic_vector(15 downto 0);
     RST                    : in  std_logic;
     CLK                    : in  std_logic
);
end delay_collatz_rev;


architecture RTL of delay_collatz_rev is
-- signal declaration
signal r                  : std_logic_vector(31 downto 0);
signal r_wire             : std_logic_vector(31 downto 0);
signal d                  : std_logic_vector(15 downto 0);
signal d_wire             : std_logic_vector(15 downto 0);
signal stop               : std_logic;
signal stop_wire          : std_logic;
signal x                  : std_logic_vector(31 downto 0);
signal d0                 : std_logic_vector(15 downto 0);
signal dd                 : std_logic_vector(15 downto 0);
signal sig_0              : std_logic_vector(31 downto 0);
signal sig_1              : std_logic_vector(31 downto 0);
signal sig_2              : std_logic_vector(31 downto 0);
signal sig_3              : std_logic_vector(31 downto 0);
signal sig_4              : std_logic_vector(31 downto 0);
signal sig_5              : std_logic_vector(31 downto 0);
signal sig_6              : std_logic;
signal sig_7              : std_logic;
signal sig_8              : std_logic;
signal sig_9              : std_logic;
signal sig_10             : std_logic;
signal sig_11             : std_logic_vector(15 downto 0);
signal sig_12             : std_logic_vector(15 downto 0);
signal sig_13             : std_logic_vector(15 downto 0);
signal done_int           : std_logic;
signal delay_int          : std_logic_vector(15 downto 0);


-- state register & states


begin
-- register updates
dpREG: process (CLK, RST)
     begin
          if (RST = '1') then
               r <= (others => '0');
               d <= (others => '0');
               stop <= '0';
          elsif CLK' event and CLK = '1' then
               r <= r_wire;
               d <= d_wire;
               stop <= stop_wire;

          end if;
     end process dpREG;


-- combinational logics
dpCMB: process (r, d, stop, x, d0, dd, sig_0, sig_1, sig_2, sig_3
, sig_4, sig_5, sig_6, sig_7, sig_8, sig_9, sig_10, sig_11, sig_12, sig_13
, done_int, delay_int, start, x0)
     begin
          r_wire <= r;
          d_wire <= d;
          stop_wire <= stop;
          x <= (others => '0');
          d0 <= (others => '0');
          dd <= (others => '0');
          sig_0 <= (others => '0');
          sig_1 <= (others => '0');
          sig_2 <= (others => '0');
          sig_3 <= (others => '0');
          sig_4 <= (others => '0');
          sig_5 <= (others => '0');
          sig_6 <= '0';
          sig_7 <= '0';
          sig_8 <= '0';
          sig_9 <= '0';
          sig_10 <= '0';
          sig_11 <= (others => '0');
          sig_12 <= (others => '0');
          sig_13 <= (others => '0');
          done_int <= '0';
          delay_int <= (others => '0');
          done <= '0';
          delay <= (others => '0');

          if (start = '1') then
               sig_0 <= std_logic_vector(resize(unsigned(x0), 32));
          else
               sig_0 <= r;
          end if;
          x <= sig_0;
          sig_1 <= std_logic_vector(shift_right(unsigned(x), 1));
          sig_2 <= std_logic_vector(unsigned(x) + unsigned(sig_1));
          sig_3 <= std_logic_vector(unsigned(sig_2) + unsigned(std_logic_vector(to_unsigned(1, 32))));
          sig_4 <= std_logic_vector(shift_right(unsigned(x), 1));
          if (x(0) = '1') then
               sig_5 <= sig_3;
          else
               sig_5 <= sig_4;
          end if;
          if (unsigned(x) = 1) then
               sig_6 <= '1';
          else
               sig_6 <= '0';
          end if;
          sig_7 <=  not start;
          sig_8 <= stop and sig_7;
          sig_9 <= sig_6 or sig_8;
          done <= done_int;
          sig_10 <= unsigned('1') + unsigned(x(0));
             --sig_10 <= std_logic_unsigned(unsigned(unsigned('1')+unsigned(x(0))));
          dd <= logic_zero_ext(sig_10, 16);
          if (start = '1') then
               sig_11 <= std_logic_vector(to_unsigned(0, 16));
          else
               sig_11 <= d;
          end if;
          d0 <= sig_11;
          sig_12 <= std_logic_vector(unsigned(d0) + unsigned(dd));
          if (done_int = '1') then
               sig_13 <= d0;
          else
               sig_13 <= sig_12;
          end if;
          delay <= delay_int;
          done_int <= sig_9;
          delay_int <= d;
          r_wire <= sig_5;
          stop_wire <= done_int;
          d_wire <= sig_13;
     end process dpCMB;

end RTL;

我对Gezel和VHDL很新，我缺少什么？

Answer 1

Gezel到VHDL生成器不会创建有效的VHDL代码，因为使用的包不支持在std_logic中添加目标，如sig_10 <= unsigned('1') + unsigned(x(0));中所示。

我想这个问题是由x中x[0]中的一个位选择为x[0]，如果为x[0]创建一个临时位，也许你可以解决这个问题，在添加之前使用sig temp_x_0 : ns(1) ; ... temp_x_0 = x[0]; dd = 1 + temp_x_0;分配此内容：

socket.emit("jwt", {
   jwt: jwt
});

但我必须承认，我对Gezel并没有那么多。

表达式的类型不明确 - “st_ulogic”或“bit”是两种可能的匹配VHDL

1 个答案: