感谢您阅读我的问题。
如果我使用＆＃34; IP目录生成一个组件＆＃34;在Vivado（2016.2）中，Vivado在我的项目中创建了以下文件夹（我为此示例生成了一个计数器）：
<proj>/ip_user_files/ip/c_counter_binary/c_counter_binary_0.veo
/c_counter_binary_0.vho
/c_counter_binary_0_stub.v
/c_counter_binary_0_stub.vhdl
<proj>/ip_user_files/ipstatic/c_addsub_v12_0_9/hdl/c_addsub_v12_0.vhd
/c_addsub_v12_0_vh_rfs.vhd
/...(and a few more)
<proj>/ip_user_files/sim_scripts/c_counter_binary_0/modelsim/compile.do
/c_counter_binary_0.sh
/simulate.do
/wave.do
(I think the rest is irrelevant for my question)
我想在ModelSim中模拟计数器。所以我想我必须运行＆＃34; c_counter_binary_0.sh＆＃34;为ModelSim生成必要的Simulation Librarys。
使用Windows 7编译这些Librarys的好方法是什么？
我现在试图在ModelSim中模拟计数器几天，但我真的不知道我接下来会尝试什么。
由于这是一个常见的想法（不是吗？），我无法理解为什么我找不到任何文档。
我尝试的事情：
使用ModelSim Transcript Console运行c_counter_binary_0.sh：
do c_counter_binary_0.sh
# ** Error: invalid command name "#!/bin/bash"
在ModelSim Transcript Console中运行文件compile.do：
do compile.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim PE vmap 10.4a Lib Mapping Utility 2015.03 Apr 7 2015
# vmap -modelsim_quiet xbip_utils_v3_0_6 msim/xbip_utils_v3_0_6
# Modifying C:/Xilinx/wkdir/lab_counter/lab_counter.ip_user_files/sim_scripts/c_counter_binary_0/modelsim/lab_counter.mpf
# Model Technology ModelSim PE vmap 10.4a Lib Mapping Utility 2015.03 Apr 7 2015
# vmap -modelsim_quiet c_reg_fd_v12_0_2 msim/c_reg_fd_v12_0_2
# Modifying C:/Xilinx/wkdir/lab_counter/lab_counter.ip_user_files/sim_scripts/c_counter_binary_0/modelsim/lab_counter.mpf
(...and so on...)
# Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr 7 2015
# Start time: 00:59:17 on Oct 31,2016
# vcom -reportprogress 300 -work xbip_utils_v3_0_6 -64 -93 ../../../ipstatic/xbip_utils_v3_0_6/hdl/xbip_utils_v3_0_vh_rfs.vhd
# -- Loading package STANDARD
# End time: 00:59:18 on Oct 31,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 1
# ** Warning: (vcom-159) Mode option -64 is not supported in this context and will be ignored.
#
(...and so on...all with no error...)
#
# Model Technology ModelSim PE Student Edition vcom 10.4a Compiler 2015.03 Apr 7 2015
# Start time: 00:59:28 on Oct 31,2016
# vcom -reportprogress 300 -work xil_defaultlib -64 -93 ../../../../lab_counter.srcs/sources_1/ip/c_counter_binary_0/sim/c_counter_binary_0.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity c_counter_binary_0
# -- Compiling architecture c_counter_binary_0_arch of c_counter_binary_0
# End time: 00:59:29 on Oct 31,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 1
但我最终得到的是空图书馆，除了：
xil_defaultlib - ＆gt; [实体] c_counter_binary_0 - ＆gt; [结构] c_counter_binary_0_arch
如果我尝试使用生成的Librarys运行模拟：
vsim work.top_tb
# vsim
# Start time: 01:08:10 on Oct 31,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.top_tb(tb)
# Loading work.top(rtl)
# Loading ieee.numeric_std(body)
# Loading work.c_counter_binary_0(c_counter_binary_0_arch)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading unisim.muxcy(muxcy_v)
# Loading unisim.xorcy(xorcy_v)
# ** Fatal: Attempting to load -nodebug design unit.
# Nodebug designs are not supported.
#
# Time: 0 ns Iteration: 0 Instance: /top_tb File: C:/Xilinx/wkdir/lab_counter/lab_counter.srcs/sim_1/imports/vhdl/tb_top.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
安装Cygwin并运行c_counter_binary_0.sh
$ ./c_counter_binary_0.sh
./c_counter_binary_0.sh: line 1: uFEFF#!/bin/bash: No such file or directory
./c_counter_binary_0.sh: line 32: $'\r': command not found
./c_counter_binary_0.sh: line 33: $'\r': command not found
c_counter_binary_0.sh - Script generated by export_simulation (Vivado v2016.2 (64-bit)-id)
./c_counter_binary_0.sh: line 36: $'\r': command not found
./c_counter_binary_0.sh: line 38: syntax error near unexpected token `$'\r''
'/c_counter_binary_0.sh: line 38: `run()
答案 0 :(得分：0)
看起来学生版本根本无法加载受保护的设备......
我的一位真正参与FPGA的朋友看了我的图书馆映射等，一切都很好......所以他用完整的Modelsim许可证测试了设计......
ModelSim PE学生版：
...
# Loading unisim.xorcy(xorcy_v)
# ** Fatal: Attempting to load -nodebug design unit.
# Nodebug designs are not supported.
#
...
使用完整许可证密钥的Modelsim：
...
# Loading unisim.xorcy(xorcy_v)
# ** Warning: (vsim-8684) No drivers exist on out port /top_tb
/DUT/c_counter_binary_0_1/U0/<protected>/<protected>/<protected>
/<protected>, and its initial value is not used.
#
...