Question

我试图通过使用for循环使用纹波进位加法器来执行加法，我希望仅在时钟的位置执行操作。为此，我使用了一个生成块并用于生成块内的循环。如果我在没有always语句的情况下使用它可以正常工作，但是当我添加always块时，它会在模拟时导致错误。以下是代码：

genvar i;
generate
    always @(posedge clk)
    for(i=0;i<=31;i=i+1) begin : generate_block         
        fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));

    end
    end

endgenerate

这里fulladd是一个不同的模块。

以下是我在模拟时得到的错误：

   Error-[IBLHS-CONST] Illegal behavioral left hand side
   add32.v, 36
   Constant Expression cannot be used on the left hand side of this assignment
   The offending expression is : i
   Source info: i = 0;


   Error-[IBLHS-CONST] Illegal behavioral left hand side
   add32.v, 36
   Constant Expression cannot be used on the left hand side of this assignment
   The offending expression is : i
   Source info: i = (i + 1);


   Error-[SE] Syntax error
   Following verilog source has syntax error :
   "add32.v", 37: token is '('
        fulladd 
   f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));

add32.v是设计模块名称。我使用了概要vcs。我是verilog编程的新手，请解释我错误的基本概念。提前致谢

Answer 1

加法逻辑＆amp;注册信号应单独处理。拉相关输入＆amp;从加法器输出信号并在posedge处单独注册。

see this CLA adder implementation code for reference

我已经实现了如下的通用纹波进位加法器。

// ripple_carry_adder.v
// NOTE : I have registered the outputs only. Inputs are asynchronous. 

`timescale 1ns  / 10 ps
module ripple_carry_adder 
            #(  parameter COUNT = 32                  // width of RCA port
            )
                (      
                    input  clk,rst,                 
                    input  Carry_in,            
                    input  [COUNT-1:0] A, B,
                    output reg [COUNT-1:0] Sum,
                    output Carry_out
                );

reg [COUNT-1:0] Carry,Cout; 
assign Carry_out = Cout[COUNT-1];

always@(posedge clk or posedge rst)
begin
    if (rst)
        begin
            Carry  = 'b0;
            Sum    = 'b0;
            Cout   = 'b0;
        end
    else
        begin   
            Cout    = ((A & B) | ((A ^ B) & Carry));
            Sum     = (A ^ B ^ Carry);
            Carry   = {Cout[COUNT-1:1],Carry_in}; 
        end
end
endmodule

Answer 2

在这种情况下，我不明白为什么你需要一个总阻挡。你永远不会在时钟的边缘实例化任何东西。

我编写生成块的方法是首先弄清楚一个实例（没有生成）会是什么样子：

fulladd f1(.sum(sum[0]),.cin(cout1[0]),.a(b[0]),.b(temp[0]),.cout(cout1[1]));

然后，将其缩放以实例化fulladd的多个实例：

genvar i;
generate
for(i=0;i<=31;i=i+1) begin : generate_block         
  fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
end
endgenerate

Verilog总是在生成块内部抛出错误

2 个答案: