System-Verilog测试平台生成2个相同频率，90度异相

Question

对于系统verilog测试平台，我需要使用参数

创建2个时钟

Clock1 = 250MHz，开始阶段0degrees

Clock2 = 250MHz，起始阶段90度，w.r.t。 CLOCK1

我尝试了以下但它对时钟生成没有影响，两者仍处于同步状态。我如何实现这种相移？

  parameter CLK_PERIOD = 4000; //250MHz = 4000ps

  initial
    Clock1 = 1'b0;
  always
    Clock1= #(CLK_PERIOD/2.0) ~Clock1;

  initial begin
    Clock2 = 1'b0;
    #1000; //to make it 90degrees out of phase with Clock1
  end
  always
    Clock2= #(CLK_PERIOD/2.0) ~Clock2;

Answer 1

在forever Clock2区块内使用initial：

module tb;
  parameter CLK_PERIOD = 4000; //250MHz = 4000ps
  bit Clock1, Clock2;
  initial
    Clock1 = 1'b0;
  always
    Clock1= #(CLK_PERIOD/2.0) ~Clock1;

  initial begin
    Clock2 = 1'b0;
    #1000; //to make it 90degrees out of phase with Clock1
    forever Clock2= #(CLK_PERIOD/2.0) ~Clock2;
  end
endmodule