Question

    module CSHM #(parameter data_width=8,order=4)
(y,in,clk,reset_n);

wire [data_width-1:0]coeff[0:order-1];
output reg signed [2*data_width-1:0]y;

input clk,reset_n;
input signed[data_width-1:0]in;
integer i;
wire [15:0] product1,product2,product3,product4,product5,product6,product7,product8;
wire signed[3:0]lsboutputcoeff;
wire signed[7:4]msboutputcoeff;
wire signed[2:0]lsbcount,msbcount;
wire signed[2:0]lsbselect,msbselect;

wire signed[2*data_width-1:0]muxoutput,shiftoutlsb,shiftoutmsb;
  wire [3:0] lsbcoeff;
  wire [7:4] msbcoeff;
    //reg [7:0] this_coeff;

wire [2:0]inputshift;
wire signed[15:0]muxout;
wire signed[15:0]leftshiftone,leftshifttwo,leftshiftthree;
wire [15:0]outputshift;




bankofprecomputers b1(.product1(product1),.product2(product2),.product3(product3),.product4(product4),.product5(product5),.product6(product6),.product7(product7),.product8(product8),.in(in));

genvar count;
generate        
 assign  coeff[0]= 8'd1;
 assign coeff[1]= 8'd2;
 assign coeff[2]= 8'd3;
 assign coeff[3]= 8'd4;
 for(count = 0; count < order ; count = count+1)
 begin : gen_loop
    assign lsbcoeff = coeff[count][3:0];
      assign msbcoeff = coeff[count][7:4];



shifter s1(.lsboutputcoeff(lsboutputcoeff),.msboutputcoeff(msboutputcoeff),.lsbselect(lsbselect),.msbselect(msbselect),.lsbcount(lsbcount),.msbcount(msbcount),.lsbcoeff(lsbcoeff),.msbcoeff(msbcoeff));
   end
endgenerate
mux8_1msb m1(.muxoutput(muxoutput),.msbselect(msbselect),.product1(product1),.product2(product2),.product3(product3),.product4(product4),.product5(product5),.product6(product6),.product7(product7),.product8(product8));

mux8_1LSB m2(.muxoutput(muxoutput),.lsbselect(lsbselect),.product1(product1),.product2(product2),.product3(product3),.product4(product4),.product5(product5),.product6(product6),.product7(product7),.product8(product8));              

inverse_shifter is1(.shiftoutmsb(shiftoutmsb),.muxoutput(muxoutput),.msbcount(msbcount));

inverse_shifter_LSB is2 (.shiftoutlsb(shiftoutlsb),.muxoutput(muxoutput),.lsbcount(lsbcount));



      always@(negedge clk)
        begin
      y = shiftoutmsb+shiftoutlsb;
          end



endmodule

当我尝试合成时，我得到错误

单位信号lsbcoeff3中的多源;这个信号是   连接到多个驱动程序。

信号lsbcoeff0中的单位多源;这个信号是   连接到多个驱动程序。

如果我错了，请指导我

Answer 1

lsbcoeff和msbcoeff在静态展开的生成循环中共享，因此您可以在这些网络上进行并行分配。要解决此问题，您需要为每个循环创建唯一的网络。这可以通过两种不同的方式完成。

对网络进行排列：

wire signed [2:0] lsbcount [0:order-1];
wire signed [2:0] msbcount [0:order-1]
for(count = 0; count < order ; count = count+1) begin : gen_loop
  assign lsbcoeff[count] = coeff[count][3:0];
  assign msbcoeff[count] = coeff[count][7:4];
  ...

通过在生成循环中声明它们来本地化网络： 注意：使用此方法，网络将无法在其循环范围之外访问。

for(count = 0; count < order ; count = count+1) begin : gen_loop
  wire signed [2:0] lsbcoeff = coeff[count][3:0];
  wire signed [2:0] msbcoeff = coeff[count][7:4];
  ...
end
// lsbcoeff and msbcoeff cannot be accessed outside of the loop

Answer 2

for 循环或多或少类似于重复n次的相同行。

for(count = 0; count < order ; count = count+1)
 begin : gen_loop
    assign lsbcoeff = coeff[count][3:0];
      assign msbcoeff = coeff[count][7:4]; 
....

所以@Suguresh，您的原始代码存在问题。

正如 Greg 正确指出的那样，您需要更正此问题。对于您的代码，解决方案1看起来更贴切。您可以更改代码并再次发布更新以重新检查吗？

verilog出错，使用generate语句编写CSHM Filter

2 个答案: