将std_logic_vector推送到变量

时间:2015-05-09 23:26:33

标签: variables vhdl

我正在尝试将两个std_logic_vector推送到函数a中的变量bdivide。 现在,问题是不会写入变量b。 但是将编写变量a,其编码方式与b相同。

我收到以下错误消息:

  

使用变量“b1”的初始值表达式,因为变量从未赋值

这是函数调用:

s_ratio <= divide((to_unsigned(0,N_CUM-4) & unsigned(hold_ratio(7 downto 4))) , (to_unsigned(0,N_CUM-4) & unsigned(hold_ratio(3 downto 0))));

这是第3行中变量b的函数。

function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
  variable a1 : unsigned(a'length-1 downto 0):=a;
  variable b1 : unsigned(b'length-1 downto 0):=b;
  variable p1 : unsigned(b'length downto 0):= (others => '0');
  variable i : integer:=0;
begin
  for i in 0 to b'length-1 loop
    p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
    p1(0) := a1(a'length-1);
    a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
    p1 := p1-b1;
    if(p1(b'length-1) ='1') then
      a1(0) :='0';
      p1 := p1+b1;
    else
      a1(0) :='1';
    end if;
  end loop;
  return a1;

end divide;

0 个答案:

没有答案