Question

我正在使用ModelSim实现一个带溢出检测的16位加法器减法器。

这是我到目前为止所拥有的。我不知道如何在加法器中实现减法器。我知道这与两个补充有关，但我不知道如何在VHDL中做到这一点。我也不确定如何进行溢出检测。

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ONE_BIT_ADDER is
  port( a, b, cin : in STD_LOGIC; 
       sum, cout : out STD_LOGIC );
end ONE_BIT_ADDER;

architecture ADDER of ONE_BIT_ADDER is 
begin

  sum <= (not a and not b and cin) or
         (not a and b and not cin) or
         (a and not b and not cin) or
         (a and b and cin);

  cout <= (not a and b and cin) or
          (a and not b and cin) or
          (a and b and not cin) or
          (a and b and cin);

end ADDER;

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SIXTEEN_BIT_ADDER is
  port( a, b : in STD_LOGIC_VECTOR(15 downto 0);
        cin : in STD_LOGIC;
        sum  : out STD_LOGIC_VECTOR(15 downto 0);
        cout, overflow : out STD_LOGIC );
end SIXTEEN_BIT_ADDER;

architecture BEHAVIORAL of SIXTEEN_BIT_ADDER is
component ONE_BIT_ADDER
  port( a, b, cin : in STD_LOGIC; 
        sum, cout : out STD_LOGIC );  
end component;

signal c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15 :    STD_LOGIC;
begin


b_adder0: ONE_BIT_ADDER port map (a => a(0), b => b(0), cin => cin, sum => sum(0), cout => c1);
b_adder1: ONE_BIT_ADDER port map (a => a(1), b => b(1), cin => c1, sum => sum(1), cout => c2);
b_adder2: ONE_BIT_ADDER port map (a => a(2), b => b(2), cin => c2, sum => sum(2), cout => c3);
b_adder3: ONE_BIT_ADDER port map (a => a(3), b => b(3), cin => c3, sum => sum(3), cout => c4);
b_adder4: ONE_BIT_ADDER port map (a => a(4), b => b(4), cin => c4, sum => sum(4), cout => c5);
b_adder5: ONE_BIT_ADDER port map (a => a(5), b => b(5), cin => c5, sum => sum(5), cout => c6);
b_adder6: ONE_BIT_ADDER port map (a => a(6), b => b(6), cin => c6, sum => sum(6), cout => c7);
b_adder7: ONE_BIT_ADDER port map (a => a(7), b => b(7), cin => c7, sum => sum(7), cout => c8);
b_adder8: ONE_BIT_ADDER port map (a => a(8), b => b(8), cin => c8, sum => sum(8), cout => c9);
b_adder9: ONE_BIT_ADDER port map (a => a(9), b => b(9), cin => c9, sum => sum(9), cout => c10);
b_adder10: ONE_BIT_ADDER port map (a => a(10), b => b(10), cin => c10, sum => sum(10), cout => c11);
b_adder11: ONE_BIT_ADDER port map (a => a(11), b => b(11), cin => c11, sum => sum(11), cout => c12);
b_adder12: ONE_BIT_ADDER port map (a => a(12), b => b(12), cin => c12, sum => sum(12), cout => c13);
b_adder13: ONE_BIT_ADDER port map (a => a(13), b => b(13), cin => c13, sum => sum(13), cout => c14);
b_adder14: ONE_BIT_ADDER port map (a => a(14), b => b(14), cin => c14, sum => sum(14), cout => c15);
b_adder15: ONE_BIT_ADDER port map (a => a(15), b => b(15), cin => c15, sum => sum(15), cout => cout);



END BEHAVIORAL;

Answer 1

您不需要使用实例。只需声明16位参数并执行操作（加或减）。假设我们有一个显示操作的参数operation。

operation = '0'（添加）

operation = '1'（减去）

现在使用以下代码（为简单起见，我从输入中删除了cin）：

LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;

ENTITY ALU IS
   PORT(data1     : IN  std_logic_vector(15 DOWNTO 0);
        data2     : IN  std_logic_vector(15 DOWNTO 0);
        operation : IN  std_logic;
        result    : OUT std_logic_vector (15 DOWNTO 0);
        overflow  : OUT std_logic
   );        
END ALU;

ARCHITECTURE Behavioral OF ALU IS
    SIGNAL result_temp : std_logic_vector(15 DOWNTO 0);
BEGIN
    result_temp <= (data1 + data2) WHEN (operation = '0') ELSE (data1 - data2);
    overflow    <= '1' WHEN (operation='0' AND data1(15)=data2(15) AND result_temp(15)/=data1(15)) or
                            (operation='1' AND data1(15)/=data2(15) AND result_temp(15)/=data1(15)) ELSE '0';
    result      <= result_temp;
END Behavioral;

关于溢出的解释：

当我们添加两个正参数时，我们预计结果为正，否则我们会溢出。

当我们添加两个负参数时，我们预计结果为负数，否则我们会溢出。

当我们减去两个参数（第一个参数是正面，第二个参数负面）时，我们预计结果正面，否则我们就会溢出。

当我们减去两个参数（第一个参数是负，第二个参数正）时，我们预计结果为负数，否则我们就会溢出。

如何使用VHDL进行溢出检测的16位加法器 - 减法器？

1 个答案: