我试图从LFSR获得64位输出。我在网上找到了一个代码并将其编辑为64位。但我没有得到输出。
module LFSR8_8E(reset_, clock, q, lfsr_to);
input clock, reset_;
output [63:0] q, lfsr_to;
reg [63:0] LFSR;
wire lfsr_to;
assign lfsr_to = (LFSR == 64'h9C69832196724182);
always @(posedge clock or negedge reset_)
begin
if (!reset_) LFSR[63:0] <= 64'h0000000000000000;
else
begin
if (lfsr_to) LFSR[63:0] <= 64'h0000000000000000;
else
begin
LFSR[63:63] <= LFSR[62:62]^LFSR[61:61];
LFSR[62:62] <= LFSR[61:61]^LFSR[60:60];
LFSR[61:61] <= LFSR[60:60]^LFSR[59:59];
LFSR[60:60] <= LFSR[59:59]^LFSR[58:58];
LFSR[59:59] <= LFSR[58:58];
LFSR[58:58] <= LFSR[57:57];
LFSR[57:57] <= LFSR[56:56];
LFSR[56:56] <= LFSR[55:55];
LFSR[54:54] <= LFSR[53:53];
LFSR[53:53] <= LFSR[52:52];
LFSR[52:52] <= LFSR[51:51];
LFSR[51:51] <= LFSR[50:50];
LFSR[49:49] <= LFSR[48:48];
LFSR[48:48] <= LFSR[47:47];
LFSR[47:47] <= LFSR[46:46];
LFSR[46:46] <= LFSR[45:45];
LFSR[45:45] <= LFSR[44:44];
LFSR[44:44] <= LFSR[43:43];
LFSR[43:43] <= LFSR[42:42];
LFSR[42:42] <= LFSR[41:41];
LFSR[41:41] <= LFSR[40:40];
LFSR[39:39] <= LFSR[38:38];
LFSR[38:38] <= LFSR[37:37];
LFSR[37:37] <= LFSR[36:36];
LFSR[36:36] <= LFSR[35:35];
LFSR[35:35] <= LFSR[34:34];
LFSR[34:34] <= LFSR[33:33];
LFSR[33:33] <= LFSR[32:32];
LFSR[32:32] <= LFSR[31:31];
LFSR[31:31] <= LFSR[30:30];
LFSR[29:29] <= LFSR[28:28];
LFSR[28:28] <= LFSR[27:27];
LFSR[27:27] <= LFSR[26:26];
LFSR[26:26] <= LFSR[25:25];
LFSR[25:25] <= LFSR[24:24];
LFSR[24:24] <= LFSR[23:23];
LFSR[23:23] <= LFSR[22:22];
LFSR[22:22] <= LFSR[21:21];
LFSR[21:21] <= LFSR[20:20];
LFSR[29:29] <= LFSR[28:28];
LFSR[28:28] <= LFSR[27:27];
LFSR[27:27] <= LFSR[26:26];
LFSR[26:26] <= LFSR[25:25];
LFSR[25:25] <= LFSR[24:24];
LFSR[24:24] <= LFSR[23:23];
LFSR[23:23] <= LFSR[22:22];
LFSR[22:22] <= LFSR[21:21];
LFSR[21:21] <= LFSR[20:20];
LFSR[20:20]<= LFSR[19:19];
LFSR[19:19] <= LFSR[18:18];
LFSR[18:18] <= LFSR[17:17];
LFSR[17:17] <= LFSR[16:16];
LFSR[16:16] <= LFSR[15:15];
LFSR[15:15] <= LFSR[14:14];
LFSR[14:14] <= LFSR[13:13];
LFSR[13:13] <= LFSR[12:12];
LFSR[12:12] <= LFSR[11:11];
LFSR[11:11] <= LFSR[10:10];
LFSR[10:10]<= LFSR[9:9];
LFSR[9:9] <= LFSR[8:8];
LFSR[8:8] <= LFSR[7:7];
LFSR[7:7] <= LFSR[6:6];
LFSR[6:6] <= LFSR[5:5];
LFSR[5:5] <= LFSR[4:4];
LFSR[4:4] <= LFSR[3:3];
LFSR[3:3] <= LFSR[2:2];
LFSR[2:2] <= LFSR[1:1];
LFSR[1:1] <= LFSR[0:0];
LFSR[0:0] <= LFSR[63:63];
end
end
end
assign q = LFSR;
endmodule
我试图获得64位输出来驱动FPGA中的64输入电路。 当我合成代码时，它省略了LFSR。
[Synth 8-3332]顺序元素（LFSR_reg [63]）未使用，将从模块LFSR8_8E中删除。（63更像这样）
任何想法如何使这个工作。
先谢谢
答案 0 :(得分：0)
LFSR的初始化值或种子对于它正常运行至关重要。在上面的设计中，您为LFSR寄存器分配了一个复位值或＆＃39; 0＆＃39;。使用＆＃39; 0＆＃39;初始值，在每个时钟边沿，通过XOR运算计算的LFSR的新值也将是“0”。因此，LFSR的值始终为＆＃39; 0＆＃39;。
综合工具解析您的代码，并发现代码中的所有操作都不会导致LFSR寄存器的值发生任何变化。因此，它会删除整个LFSR寄存器，这就是您看到警告[Synth 8-3332]
的原因LFSR永远不应该具有全零值。如果我将重置值修改为64＆＃39; hffff_ffff_ffff_ffff，则LFSR可以正常工作。
修改后的代码如下。
module LFSR8_8E(reset_, clock, q, lfsr_to);
input clock, reset_;
output [63:0] q;
output lfsr_to;
reg [63:0] LFSR;
wire lfsr_to;
assign lfsr_to = (LFSR == 64'h9C69832196724182);
always @(posedge clock or negedge reset_)
begin
if (!reset_)
LFSR[63:0] <= 64'hffff_ffff_ffff_ffff;
else if (lfsr_to)
LFSR[63:0] <= 64'hffff_ffff_ffff_ffff;
else
begin
LFSR[63:0] <= {(LFSR[62]^LFSR[61]),
(LFSR[61]^LFSR[60]),
(LFSR[60]^LFSR[59]),
(LFSR[59]^LFSR[58]),
LFSR[58:0],
LFSR[63]};
end
end
assign q = LFSR;
endmodule
我想指出的另一件事是，如果LFSR是最大长度LFSR，那么条件
else if (lfsr_to)
LFSR[63:0] <= 64'hffff_ffff_ffff_ffff;
没有必要。 LFSR寄存器将自动翻转到初始值。看一下代码，我估计LFSR多项式不会产生最大长度。 您可能想查看Wikipedia
上的一些标准LFSR多项式在这里查看您在EDA游乐场的设计模拟 https://www.edaplayground.com/x/5NpK
如果您需要根据外部信号禁用LFSR，可以在https://www.edaplayground.com/x/n7Q
处获得修改后的代码